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    <title>topic Need help, SIMD guru in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/Need-help-SIMD-guru/m-p/800229#M607</link>
    <description>Hello All,&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;I am coding a SIMD program (under AMS), I do not succeed my final arrangement of one of&lt;/DIV&gt;&lt;DIV&gt;my xmm register. In this 128 bits register, I have 4 double words (int) like that :&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="white-space: pre;"&gt;	&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="white-space: pre;"&gt;&lt;SPAN style="white-space: pre;"&gt;					&lt;/SPAN&gt;A&lt;/SPAN&gt;B C D&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;I would like reorder the register like that :&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="white-space: pre;"&gt;					&lt;/SPAN&gt;0 A B C&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;it seems to be the asm pshufd xmm, xmm, imm8. But I do not find the magical value at imm8, although&lt;/DIV&gt;&lt;DIV&gt;I read ten times the doc ...&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Thank you&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Tim&lt;/DIV&gt;</description>
    <pubDate>Mon, 25 Oct 2010 16:37:12 GMT</pubDate>
    <dc:creator>Timocafe</dc:creator>
    <dc:date>2010-10-25T16:37:12Z</dc:date>
    <item>
      <title>Need help, SIMD guru</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Need-help-SIMD-guru/m-p/800229#M607</link>
      <description>Hello All,&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;I am coding a SIMD program (under AMS), I do not succeed my final arrangement of one of&lt;/DIV&gt;&lt;DIV&gt;my xmm register. In this 128 bits register, I have 4 double words (int) like that :&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="white-space: pre;"&gt;	&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="white-space: pre;"&gt;&lt;SPAN style="white-space: pre;"&gt;					&lt;/SPAN&gt;A&lt;/SPAN&gt;B C D&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;I would like reorder the register like that :&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN style="white-space: pre;"&gt;					&lt;/SPAN&gt;0 A B C&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;it seems to be the asm pshufd xmm, xmm, imm8. But I do not find the magical value at imm8, although&lt;/DIV&gt;&lt;DIV&gt;I read ten times the doc ...&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Thank you&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Tim&lt;/DIV&gt;</description>
      <pubDate>Mon, 25 Oct 2010 16:37:12 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Need-help-SIMD-guru/m-p/800229#M607</guid>
      <dc:creator>Timocafe</dc:creator>
      <dc:date>2010-10-25T16:37:12Z</dc:date>
    </item>
    <item>
      <title>Need help, SIMD guru</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Need-help-SIMD-guru/m-p/800230#M608</link>
      <description>It is much easier to shift in this case (and the correct direction depends on whether you noted memory order or order inside the register - which is just the opposite thanks to little endian x86...)&lt;BR /&gt;&lt;BR /&gt;v = _mm_slli_si128(v, 4); // shift the contents of v to the left by 4 bytes&lt;BR /&gt;&lt;BR /&gt;or&lt;BR /&gt;&lt;BR /&gt;v = _mm_srli_si128(v, 4); // shift to the right by 4 bytes&lt;BR /&gt;&lt;BR /&gt;The little endian confusion is probably also what makes it so hard to get the correct number for pshufd...</description>
      <pubDate>Mon, 25 Oct 2010 17:06:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Need-help-SIMD-guru/m-p/800230#M608</guid>
      <dc:creator>Matthias_Kretz</dc:creator>
      <dc:date>2010-10-25T17:06:24Z</dc:date>
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    <item>
      <title>Need help, SIMD guru</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Need-help-SIMD-guru/m-p/800231#M609</link>
      <description>Thank you very much, it works. As it was a Microsoft specific "functions", I believed it will not work under GCC or ICC. Do we get a convergence between Microsoft/Intel/AMD SIMD ? My reference book is the software&lt;DIV&gt;Vectorization handbook it is on intel SSE2 that why I do not find the reference if this function.&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Regard's&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Tim&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Tue, 26 Oct 2010 09:16:49 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Need-help-SIMD-guru/m-p/800231#M609</guid>
      <dc:creator>Timocafe</dc:creator>
      <dc:date>2010-10-26T09:16:49Z</dc:date>
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    <item>
      <title>Need help, SIMD guru</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Need-help-SIMD-guru/m-p/800232#M610</link>
      <description>&lt;P&gt;As these are intrinsics they should work under any of these compilers (MSVC, ICC or GCC) without problems. However, as you go to the latest and greatest intrinsics the compiler support will probably differ but eventually all compilers will end up addingthat support (just at different points in time).&lt;/P&gt;</description>
      <pubDate>Tue, 26 Oct 2010 09:57:19 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Need-help-SIMD-guru/m-p/800232#M610</guid>
      <dc:creator>Nicolae_P_Intel</dc:creator>
      <dc:date>2010-10-26T09:57:19Z</dc:date>
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    <item>
      <title>Need help, SIMD guru</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Need-help-SIMD-guru/m-p/800233#M611</link>
      <description>There are differences among the compilers in flexibility of syntax. For example, Intel supports some nesting of intrinsics which Microsoft doesn't, while gcc is more flexible about 128-bit integer usage. Intel compilers have dropped &lt;XMMINTRIN.H&gt; as there no longer is support for SSE without SSE2.&lt;BR /&gt;I think a few cases which Microsoft supported but Intel didn't were in line to be fixed.&lt;/XMMINTRIN.H&gt;</description>
      <pubDate>Tue, 26 Oct 2010 13:27:49 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Need-help-SIMD-guru/m-p/800233#M611</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2010-10-26T13:27:49Z</dc:date>
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