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    <title>topic https://en.wikipedia.org/wiki in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/Cache-L1-L2-L3/m-p/1113187#M6123</link>
    <description>&lt;P&gt;&lt;A href="https://en.wikipedia.org/wiki/Cache_memory"&gt;https://en.wikipedia.org/wiki/Cache_memory&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;Jim Dempsey&lt;/P&gt;</description>
    <pubDate>Tue, 07 Mar 2017 22:05:01 GMT</pubDate>
    <dc:creator>jimdempseyatthecove</dc:creator>
    <dc:date>2017-03-07T22:05:01Z</dc:date>
    <item>
      <title>Cache L1 , L2 , L3 ?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Cache-L1-L2-L3/m-p/1113186#M6122</link>
      <description>&lt;P&gt;what does L1 ( instruction , data ) , L2 , L3 mean ?&lt;/P&gt;</description>
      <pubDate>Tue, 07 Mar 2017 18:59:43 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Cache-L1-L2-L3/m-p/1113186#M6122</guid>
      <dc:creator>RBato</dc:creator>
      <dc:date>2017-03-07T18:59:43Z</dc:date>
    </item>
    <item>
      <title>https://en.wikipedia.org/wiki</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Cache-L1-L2-L3/m-p/1113187#M6123</link>
      <description>&lt;P&gt;&lt;A href="https://en.wikipedia.org/wiki/Cache_memory"&gt;https://en.wikipedia.org/wiki/Cache_memory&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;Jim Dempsey&lt;/P&gt;</description>
      <pubDate>Tue, 07 Mar 2017 22:05:01 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Cache-L1-L2-L3/m-p/1113187#M6123</guid>
      <dc:creator>jimdempseyatthecove</dc:creator>
      <dc:date>2017-03-07T22:05:01Z</dc:date>
    </item>
    <item>
      <title>Rafal,</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Cache-L1-L2-L3/m-p/1113188#M6124</link>
      <description>&lt;P&gt;Rafal,&lt;/P&gt;

&lt;P&gt;The following article written by&amp;nbsp;Chris Gottbrath a few years ago and published on Dr. Dobb's is very useful to understand processor caches. It was written before Intel launched the first Xeon Phi. However, it is still very useful. The following is the link:&amp;nbsp;&lt;A href="http://www.drdobbs.com/parallel/cache-friendly-code-solving-manycores-ne/240012736"&gt;http://www.drdobbs.com/parallel/cache-friendly-code-solving-manycores-ne/240012736&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 03 Apr 2017 02:49:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Cache-L1-L2-L3/m-p/1113188#M6124</guid>
      <dc:creator>gaston-hillar</dc:creator>
      <dc:date>2017-04-03T02:49:06Z</dc:date>
    </item>
    <item>
      <title>Rafal,</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Cache-L1-L2-L3/m-p/1113189#M6125</link>
      <description>&lt;P&gt;Rafal,&lt;/P&gt;

&lt;P&gt;Another article that you must read and is written by the same person that provided the first answer for your thread: Jim Dempsey (jimdempseytatthecove).&lt;/P&gt;

&lt;P&gt;The article has a few years but it is a must read (short but useful article).&amp;nbsp;&lt;A href="http://www.drdobbs.com/parallel/superscalar-programming-with-hyperthread/228800471?queryText=l3%2Bcache"&gt;Superscalar Programming with HyperThreading and Shared Cache Systems&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 03 Apr 2017 02:58:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Cache-L1-L2-L3/m-p/1113189#M6125</guid>
      <dc:creator>gaston-hillar</dc:creator>
      <dc:date>2017-04-03T02:58:06Z</dc:date>
    </item>
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