topic I am looking in to your SDM in Intel® ISA Extensions

permitted CR2 values

Beulich__Jan — Tue, 12 Feb 2019 10:49:49 GMT

Hello,

AVX512 instructions allowing memory fault suppression as well as V{,P}MASKMOV* are not well specified in terms of the CR2 values they may produce upon raising #PF for non-sequential enabled elements, especially when a page boundary is crossed within a range of disabled elements. Could it be made explicit whether the observable behavior on available hardware is the only permitted pattern, or whether e.g. more relaxed constraints apply here? (It's been a while since I've tried out V{,P}MASKMOV*, but iirc Intel and AMD hardware behavior actually disagrees in some specific cases, which suggests that some relaxation would likely better to be put in effect anyway.)

Thanks, Jan

Hi Jan, good question. We'll

MarkC_Intel — Wed, 27 Feb 2019 13:54:58 GMT

Hi Jan, good question. We'll have to think about this one and get back to you.

Hi Jan, did some poking

MarkC_Intel — Wed, 06 Mar 2019 18:59:08 GMT

Hi Jan, did some poking around. The sub-page bits in CR2 are implementation defined.

Thanks Mark! Any chance this

Beulich__Jan — Thu, 07 Mar 2019 10:49:08 GMT

Thanks Mark! Any chance this could be stated by the SDM (unless it is already and I simply was unable to find it)?

I am looking in to your SDM

MarkC_Intel — Fri, 08 Mar 2019 14:03:11 GMT

I am looking in to your SDM update request.