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    <title>topic Re: AMX support in SDE incomplete? in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1193848#M6817</link>
    <description>&lt;P&gt;And to add to the apparent mess&lt;/P&gt;
&lt;P&gt;- leaf 0 EAX = 1A (i.e. no leaves 1D and 1E)&lt;/P&gt;
&lt;P&gt;Otoh leaf 7 subleaf 0 EAX has bits 17 and 18 set.&lt;/P&gt;</description>
    <pubDate>Tue, 21 Jul 2020 09:23:50 GMT</pubDate>
    <dc:creator>Beulich__Jan</dc:creator>
    <dc:date>2020-07-21T09:23:50Z</dc:date>
    <item>
      <title>AMX support in SDE incomplete?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1193846#M6816</link>
      <description>&lt;P&gt;Looking at CPUID output with -spr I notice&lt;/P&gt;
&lt;P&gt;- leaf 7 subleaf 0 EDX bits 24 and 25 set, but bit 22 clear (i.e. no AMX-BF16)&lt;/P&gt;
&lt;P&gt;- leaf D subleaf 0 ECX being 0xA80 (i.e. covering just the low 8 XCR0 bits)&lt;/P&gt;
&lt;P&gt;- leaf D subleaf 17 and 18 entirely empty&lt;/P&gt;
&lt;P&gt;Is this intentional?&lt;/P&gt;</description>
      <pubDate>Tue, 21 Jul 2020 09:11:51 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1193846#M6816</guid>
      <dc:creator>Beulich__Jan</dc:creator>
      <dc:date>2020-07-21T09:11:51Z</dc:date>
    </item>
    <item>
      <title>Re: AMX support in SDE incomplete?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1193848#M6817</link>
      <description>&lt;P&gt;And to add to the apparent mess&lt;/P&gt;
&lt;P&gt;- leaf 0 EAX = 1A (i.e. no leaves 1D and 1E)&lt;/P&gt;
&lt;P&gt;Otoh leaf 7 subleaf 0 EAX has bits 17 and 18 set.&lt;/P&gt;</description>
      <pubDate>Tue, 21 Jul 2020 09:23:50 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1193848#M6817</guid>
      <dc:creator>Beulich__Jan</dc:creator>
      <dc:date>2020-07-21T09:23:50Z</dc:date>
    </item>
    <item>
      <title>Re: AMX support in SDE incomplete?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1193863#M6818</link>
      <description>&lt;P&gt;I'm sorry - I was wrong with "leaf 7 subleaf 0 EDX bits 24 and 25 set, but bit 22 clear (i.e. no AMX-BF16)"; apparently I couldn't count. All other aspects look to apply, though.&lt;/P&gt;</description>
      <pubDate>Tue, 21 Jul 2020 10:30:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1193863#M6818</guid>
      <dc:creator>Beulich__Jan</dc:creator>
      <dc:date>2020-07-21T10:30:52Z</dc:date>
    </item>
    <item>
      <title>Re: AMX support in SDE incomplete?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1194104#M6819</link>
      <description>&lt;P&gt;This is not intention, I'll review the CPUID definition for all the AMX features.&lt;/P&gt;</description>
      <pubDate>Wed, 22 Jul 2020 15:08:38 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1194104#M6819</guid>
      <dc:creator>AdyT_Intel</dc:creator>
      <dc:date>2020-07-22T15:08:38Z</dc:date>
    </item>
    <item>
      <title>Re: AMX support in SDE incomplete?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1194106#M6820</link>
      <description>&lt;P&gt;I checked the CPUID definition for Sapphire Rapids CPU and I found that the bits are correct.&lt;/P&gt;
&lt;P&gt;This means:&lt;BR /&gt;- Leaf 7 sub-leaf 0&amp;nbsp; =&amp;gt; EDX is 0x03554110 (bits 22,24,25 are set).&lt;BR /&gt;- Leaf 0xd sub -leaf 0 =&amp;gt; EAX is 0x600ff (bits 17/18 are set)&lt;BR /&gt;&lt;BR /&gt;However, the current version of Intel SDE (8.56) does not support XSAVE/XRSTOR&amp;nbsp; for the AMX data and does not emulate the XFD feature.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Please note that this CPUID definition is available under the -spr CPU knob.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 22 Jul 2020 15:50:23 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1194106#M6820</guid>
      <dc:creator>AdyT_Intel</dc:creator>
      <dc:date>2020-07-22T15:50:23Z</dc:date>
    </item>
    <item>
      <title>Re: AMX support in SDE incomplete?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1194107#M6821</link>
      <description>&lt;P&gt;I did check with -spr, yes. Bits 17 and 18 set in D:0:EAX implies subleaves 17 and 18 also supplying non-zero output, aiui.&lt;/P&gt;
&lt;P&gt;What's more important for my immediate purpose though are leaves 1D and 1E, which are missing altogether (due to the highest leave reported being 14 iirc). Without these I can't determine tile valid configuration(s).&lt;/P&gt;</description>
      <pubDate>Wed, 22 Jul 2020 15:58:58 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1194107#M6821</guid>
      <dc:creator>Beulich__Jan</dc:creator>
      <dc:date>2020-07-22T15:58:58Z</dc:date>
    </item>
    <item>
      <title>Re: AMX support in SDE incomplete?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1194113#M6822</link>
      <description>&lt;P&gt;Yes, you are correct. We did miss updating the value for the max leaf reported (i.e. leaf 0 - EAX).&lt;/P&gt;
&lt;P&gt;You can fix it yourself by editing the CPUID definition file for SPR (this is a text file in the kit).&lt;/P&gt;
&lt;P&gt;The file is under the: misc/cpuid/spr/cpuid.def directory in the kit. The file format is quite simple. Just edit the entry for leaf 0 and put 1e instead of the current value of 14.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks for reporting this. We will fix it for next release.&lt;/P&gt;</description>
      <pubDate>Wed, 22 Jul 2020 16:10:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1194113#M6822</guid>
      <dc:creator>AdyT_Intel</dc:creator>
      <dc:date>2020-07-22T16:10:56Z</dc:date>
    </item>
    <item>
      <title>Re: AMX support in SDE incomplete?</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1194221#M6823</link>
      <description>&lt;P&gt;Ah, interesting, thanks. This then also allowed me to fix leaf &lt;LI-EMOJI id="lia_anguished-face" title=":anguished_face:"&gt;&lt;/LI-EMOJI&gt; The file specifies subleaves hex 17 and 18, when it should be hex 11 and 12 (dec 17 and 18).&lt;/P&gt;
&lt;P&gt;There are also similar max leaf issues in other files - I've changed skl, snr, and tnt here, but I think I saw a few more where I simply thought I didn't care for now.&lt;/P&gt;</description>
      <pubDate>Thu, 23 Jul 2020 06:28:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/AMX-support-in-SDE-incomplete/m-p/1194221#M6823</guid>
      <dc:creator>Beulich__Jan</dc:creator>
      <dc:date>2020-07-23T06:28:52Z</dc:date>
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