<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: APX vs EFLAGS.AF in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/APX-vs-EFLAGS-AF/m-p/1707776#M7157</link>
    <description>&lt;P&gt;Thanks, Jan.&amp;nbsp; Solid feedback.&amp;nbsp; Here's my take on this, from my point-of-view.&lt;BR /&gt;&lt;BR /&gt;In general, we always have x86-64 simplifications in mind, but we also are cognizant of the scope/cost/complexity of clean-up efforts and their impacts on SW intricacy, HW validation, power/perf gain, value, etc.&amp;nbsp; When x86-64 (or any modal feature) is added, it provides a blanket way of making changes easier, as they're local to that mode, but this was not pursued as x86-64 was introduced.&amp;nbsp;&amp;nbsp;Since APX is not modal, there isn't as much freedom to alter semantics, either, and we didn't pursue such changes.&lt;BR /&gt;&lt;BR /&gt;In cases like this, we purposefully wanted to design APX with minimal perturbance in that we didn't want instructions to change semantics (unless it was useful**) just because they use an APX-related prefix; esp. as register allocation (and use of EGPRs, NDD, etc.) may be outside of the control of a SW developer.&amp;nbsp;&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;In addition, from a hardware perspective, APX is not really adding much in the way of new functional units -- rather much of it is just new encodings for things that the underlying machine, and the underlying uOPs, already support.&amp;nbsp; So, APX (aside from the _new_ instructions APX introduces) seeks to map efficiently to the existing uOPs, rather than inventing new uOPs, with ever-so-slightly modified semantics.&amp;nbsp; From a definition/test/validation perspective, for both Intel and others, this also means that definitions, usages, and validation tests for a legacy-encoded op that writes EFLAGS.AF can also be leveraged for the REX2 and EVEX versions of said instructions. So, even if AF isn't popular and is often un-used, or even un-defined (although most implementations have a defined behavior that doesn't really deviate), the cost of changing it's semantics outweighs visible benefits.&lt;BR /&gt;&lt;BR /&gt;**I will say that we did pursue "useful" semantic changes in APX, esp. with respect to NDD operation's having zero-upper semantics in smaller bit-width operations.&amp;nbsp; The merge behavior is often not desired by software, and the cost of merge behavior at the HW level requires additional sources/dependencies, etc.&lt;/P&gt;</description>
    <pubDate>Wed, 06 Aug 2025 15:22:17 GMT</pubDate>
    <dc:creator>j_agron</dc:creator>
    <dc:date>2025-08-06T15:22:17Z</dc:date>
    <item>
      <title>APX vs EFLAGS.AF</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/APX-vs-EFLAGS-AF/m-p/1700375#M7153</link>
      <description>&lt;P&gt;Would it be possible (and make sense) to alter the APX spec slightly to state that whenever it's not left alone by an insn, AF is undefined? APX being 64-bit only, and EFLAGS.AF - aiui - being largely meaningless in 64-bit mode would seem to suggest that such a slight adjustment could already have been done when x86-64 was first specified. While that can't be altered anymore, new 64-bit-only ISA extensions certainly have some playing room there ...&lt;/P&gt;</description>
      <pubDate>Sun, 29 Jun 2025 14:16:42 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/APX-vs-EFLAGS-AF/m-p/1700375#M7153</guid>
      <dc:creator>Beulich__Jan</dc:creator>
      <dc:date>2025-06-29T14:16:42Z</dc:date>
    </item>
    <item>
      <title>Re: APX vs EFLAGS.AF</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/APX-vs-EFLAGS-AF/m-p/1707776#M7157</link>
      <description>&lt;P&gt;Thanks, Jan.&amp;nbsp; Solid feedback.&amp;nbsp; Here's my take on this, from my point-of-view.&lt;BR /&gt;&lt;BR /&gt;In general, we always have x86-64 simplifications in mind, but we also are cognizant of the scope/cost/complexity of clean-up efforts and their impacts on SW intricacy, HW validation, power/perf gain, value, etc.&amp;nbsp; When x86-64 (or any modal feature) is added, it provides a blanket way of making changes easier, as they're local to that mode, but this was not pursued as x86-64 was introduced.&amp;nbsp;&amp;nbsp;Since APX is not modal, there isn't as much freedom to alter semantics, either, and we didn't pursue such changes.&lt;BR /&gt;&lt;BR /&gt;In cases like this, we purposefully wanted to design APX with minimal perturbance in that we didn't want instructions to change semantics (unless it was useful**) just because they use an APX-related prefix; esp. as register allocation (and use of EGPRs, NDD, etc.) may be outside of the control of a SW developer.&amp;nbsp;&amp;nbsp;&lt;BR /&gt;&lt;BR /&gt;In addition, from a hardware perspective, APX is not really adding much in the way of new functional units -- rather much of it is just new encodings for things that the underlying machine, and the underlying uOPs, already support.&amp;nbsp; So, APX (aside from the _new_ instructions APX introduces) seeks to map efficiently to the existing uOPs, rather than inventing new uOPs, with ever-so-slightly modified semantics.&amp;nbsp; From a definition/test/validation perspective, for both Intel and others, this also means that definitions, usages, and validation tests for a legacy-encoded op that writes EFLAGS.AF can also be leveraged for the REX2 and EVEX versions of said instructions. So, even if AF isn't popular and is often un-used, or even un-defined (although most implementations have a defined behavior that doesn't really deviate), the cost of changing it's semantics outweighs visible benefits.&lt;BR /&gt;&lt;BR /&gt;**I will say that we did pursue "useful" semantic changes in APX, esp. with respect to NDD operation's having zero-upper semantics in smaller bit-width operations.&amp;nbsp; The merge behavior is often not desired by software, and the cost of merge behavior at the HW level requires additional sources/dependencies, etc.&lt;/P&gt;</description>
      <pubDate>Wed, 06 Aug 2025 15:22:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/APX-vs-EFLAGS-AF/m-p/1707776#M7157</guid>
      <dc:creator>j_agron</dc:creator>
      <dc:date>2025-08-06T15:22:17Z</dc:date>
    </item>
  </channel>
</rss>

