topic Non-AVX opcodes in Intel® ISA Extensions

Non-AVX opcodes

aorl — Fri, 30 Jul 2010 16:12:28 GMT

Hi.

I was just reading "Intel Advanced Vector Extensions Programming Reference" for the first time and a few questions popped up immediately after readingsection 4. Maybe some reader in this forum can help me out.

1) does VEX prefix allow any type of prefix before it ? According to section 4.1.1, 4.1.2 and 4.1.3 I understand that no prefix is allowed, but figure 4-1 suggests the opposite
2) can I use the VEX prefix to encode an instruction like for example RDTSC (0F 31)?

Thank you.

Non-AVX opcodes

Brijender_B_Intel — Fri, 30 Jul 2010 17:40:59 GMT

The good thing about VEX encoding is that it has compacted the encoding and added the possibility of adding more opcodes. The usual SIMD perfixes 0F, 66, F2 F3 etc are encoded in 2nd or 3rd byte of the VEX. However when you decode those instructions these prefixes are present. You can not encode RDTSC with VEX.
VEX perfix is only valid for AVX instructions - SIMD instructions (encoded in VEX form).

Non-AVX opcodes

aorl — Fri, 30 Jul 2010 17:53:10 GMT

It's more clear now ! Thank you for your reply.

Non-AVX opcodes

knujohn4 — Sat, 07 Aug 2010 16:42:35 GMT

It looks like prefixes from "group1" (Lock and Repeat prefixes) is not allowed. Prefixes from "group2" (Segment overrides) are allowed and Operand size overridenot allowed but address size override (0x67) is.

Knut