<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Intrinsic guide 2.6 error in documentation in Intel® ISA Extensions</title>
    <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intrinsic-guide-2-6-error-in-documentation/m-p/812901#M912</link>
    <description>14 bits is correct. See the Instruction Set Reference in the Software Developer's Manual:&lt;A title="http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html" href="http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html"&gt;http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html&lt;/A&gt;&lt;DIV&gt;&lt;SPAN style="font-family: Verdana, Arial, Helvetica, sans-serif;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV class="column"&gt;
			&lt;P&gt;&lt;B&gt;PMULHRSW (with 128-bit operand)
&lt;/B&gt;&lt;/P&gt;
			&lt;P&gt;temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) &amp;gt;&amp;gt;14) + 1;&lt;BR /&gt;temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;temp3[31:0] = INT32 ((DEST[63:48] * SRC[63:48]) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;temp4[31:0] = INT32 ((DEST[79:64] * SRC[79:64]) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;temp5[31:0] = INT32 ((DEST[95:80] * SRC[95:80]) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;temp6[31:0] = INT32 ((DEST[111:96] * SRC[111:96]) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;temp7[31:0] = INT32 ((DEST[127:112] * SRC[127:112) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;DEST[15:0] = temp0[16:1];&lt;BR /&gt;DEST[31:16] = temp1[16:1];
&lt;BR /&gt;DEST[47:32] = temp2[16:1];
&lt;BR /&gt;DEST[63:48] = temp3[16:1];
&lt;BR /&gt;DEST[79:64] = temp4[16:1];
&lt;BR /&gt;DEST[95:80] = temp5[16:1];
&lt;BR /&gt;DEST[111:96] = temp6[16:1];
&lt;BR /&gt;DEST[127:112] = temp7[16:1];&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
    <pubDate>Mon, 13 Feb 2012 17:48:57 GMT</pubDate>
    <dc:creator>Patrick_K_Intel</dc:creator>
    <dc:date>2012-02-13T17:48:57Z</dc:date>
    <item>
      <title>Intrinsic guide 2.6 error in documentation</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intrinsic-guide-2-6-error-in-documentation/m-p/812900#M911</link>
      <description>&lt;P&gt;In the documentation the intrinsic _mm_mulhrs_epi16 the shift right should be 15 and not 14.&lt;/P&gt;</description>
      <pubDate>Thu, 09 Feb 2012 08:29:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intrinsic-guide-2-6-error-in-documentation/m-p/812900#M911</guid>
      <dc:creator>gilgil</dc:creator>
      <dc:date>2012-02-09T08:29:45Z</dc:date>
    </item>
    <item>
      <title>Intrinsic guide 2.6 error in documentation</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intrinsic-guide-2-6-error-in-documentation/m-p/812901#M912</link>
      <description>14 bits is correct. See the Instruction Set Reference in the Software Developer's Manual:&lt;A title="http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html" href="http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html"&gt;http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html&lt;/A&gt;&lt;DIV&gt;&lt;SPAN style="font-family: Verdana, Arial, Helvetica, sans-serif;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV class="column"&gt;
			&lt;P&gt;&lt;B&gt;PMULHRSW (with 128-bit operand)
&lt;/B&gt;&lt;/P&gt;
			&lt;P&gt;temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) &amp;gt;&amp;gt;14) + 1;&lt;BR /&gt;temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;temp3[31:0] = INT32 ((DEST[63:48] * SRC[63:48]) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;temp4[31:0] = INT32 ((DEST[79:64] * SRC[79:64]) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;temp5[31:0] = INT32 ((DEST[95:80] * SRC[95:80]) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;temp6[31:0] = INT32 ((DEST[111:96] * SRC[111:96]) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;temp7[31:0] = INT32 ((DEST[127:112] * SRC[127:112) &amp;gt;&amp;gt;14) + 1;
&lt;BR /&gt;DEST[15:0] = temp0[16:1];&lt;BR /&gt;DEST[31:16] = temp1[16:1];
&lt;BR /&gt;DEST[47:32] = temp2[16:1];
&lt;BR /&gt;DEST[63:48] = temp3[16:1];
&lt;BR /&gt;DEST[79:64] = temp4[16:1];
&lt;BR /&gt;DEST[95:80] = temp5[16:1];
&lt;BR /&gt;DEST[111:96] = temp6[16:1];
&lt;BR /&gt;DEST[127:112] = temp7[16:1];&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Mon, 13 Feb 2012 17:48:57 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intrinsic-guide-2-6-error-in-documentation/m-p/812901#M912</guid>
      <dc:creator>Patrick_K_Intel</dc:creator>
      <dc:date>2012-02-13T17:48:57Z</dc:date>
    </item>
    <item>
      <title>Intrinsic guide 2.6 error in documentation</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intrinsic-guide-2-6-error-in-documentation/m-p/812902#M913</link>
      <description>&lt;P&gt;I still do not understand...&lt;BR /&gt;&lt;BR /&gt;I try the next piece of code&lt;BR /&gt;float factor = 1.f;&lt;BR /&gt;__m128i vFactor = _mm_set1_epi16(factor*(1&amp;lt;&amp;lt;14)); // Using fixed point..&lt;/P&gt;&lt;P&gt;__m128i inputVec = _mm_set_epi16(32,54,124,75,35,235,244,36);&lt;/P&gt;&lt;P&gt;__m128i resultVec = _mm_mulhrs_epi16(inputVec,vFactor);&lt;BR /&gt;&lt;BR /&gt;By your explanation I should get resultVec = inputVec but the result elements are actually half the original values..&lt;/P&gt;</description>
      <pubDate>Thu, 10 May 2012 09:35:42 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intrinsic-guide-2-6-error-in-documentation/m-p/812902#M913</guid>
      <dc:creator>gilgil</dc:creator>
      <dc:date>2012-05-10T09:35:42Z</dc:date>
    </item>
    <item>
      <title>Intrinsic guide 2.6 error in documentation</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intrinsic-guide-2-6-error-in-documentation/m-p/812903#M914</link>
      <description>If you carefully read the documentation you will notice an additional hidden shift by 1.&lt;BR /&gt;The temp*[16:1] can be read as (temp*[31:0]&amp;gt;&amp;gt;1)[15:0].&lt;BR /&gt;&lt;BR /&gt;It might make sense to make the documentation more evident about this.&lt;BR /&gt;</description>
      <pubDate>Thu, 10 May 2012 09:51:11 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intrinsic-guide-2-6-error-in-documentation/m-p/812903#M914</guid>
      <dc:creator>sirrida</dc:creator>
      <dc:date>2012-05-10T09:51:11Z</dc:date>
    </item>
    <item>
      <title>Intrinsic guide 2.6 error in documentation</title>
      <link>https://community.intel.com/t5/Intel-ISA-Extensions/Intrinsic-guide-2-6-error-in-documentation/m-p/812904#M915</link>
      <description>I agree the documentation for this function is not the best one.</description>
      <pubDate>Thu, 10 May 2012 10:03:58 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-ISA-Extensions/Intrinsic-guide-2-6-error-in-documentation/m-p/812904#M915</guid>
      <dc:creator>gilgil</dc:creator>
      <dc:date>2012-05-10T10:03:58Z</dc:date>
    </item>
  </channel>
</rss>

