<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic About lockfreE_mpmc ..... in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/About-lockfreE-mpmc/m-p/769202#M105</link>
    <description>&lt;DIV&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;BR /&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;I wrote:&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&amp;gt; Hello all,&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; I think i have discovered a problem 
with lockfree_mpmc:&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; You will find the source code of 
lockfree_mpmc at:&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; &lt;A href="http://pages.videotron.com/aminer/"&gt;http://pages.videotron.com/aminer/&lt;/A&gt;&lt;BR /&gt;&amp;gt; 
&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; So please follow with me:&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; If you take a look 
at the lockfree_mpmc , here is&amp;nbsp; the source code&lt;BR /&gt;&amp;gt; of the push() 
method:&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; ---&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; function TLockfree_MPMC.push(tm : 
tNodeQueue):boolean;&lt;BR /&gt;&amp;gt; var lasttail,newtemp:long;&lt;BR /&gt;&amp;gt; 
i,j:integer;&lt;BR /&gt;&amp;gt; begin&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt;&amp;nbsp;if getlength &amp;gt;= fsize&lt;BR /&gt;&amp;gt;&amp;nbsp; 
then&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; begin&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; result:=false;&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
exit;&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; end;&lt;BR /&gt;&amp;gt; result:=true;&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; 
newTemp:=LockedIncLong(temp);&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; [1] lastTail:=newTemp-1;&lt;BR /&gt;&amp;gt; 
[2] setObject(lastTail,tm);&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; repeat&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt;&amp;nbsp;if 
CAS(tail,lasttail,newtemp)&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp; then&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; begin&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
exit;&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; end;&lt;BR /&gt;&amp;gt; sleep(0);&lt;BR /&gt;&amp;gt;&amp;nbsp;until false;&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; 
end;&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; ---&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; As you know in the x86 architecture 
Loads may be reordered with older stores&lt;BR /&gt;&amp;gt; to different locations.&lt;BR /&gt;&amp;gt; 
&lt;BR /&gt;&amp;gt; So in line [2] there is a load of tail and lasttail to the registers of 
the &lt;BR /&gt;&amp;gt; processor&lt;BR /&gt;&amp;gt; before calling setobject() and just before on 
line [1] there is a store to &lt;BR /&gt;&amp;gt; lasttail.&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; So as you have 
noticed the processor can then reorder the loads on line [2] &lt;BR /&gt;&amp;gt; with the 
older&lt;BR /&gt;&amp;gt; store on line [1] and this will cause a problem, so i think i have 
to insert &lt;BR /&gt;&amp;gt; an mfence between&lt;BR /&gt;&amp;gt; line [1] and line [2].&lt;BR /&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;BR /&gt;In the&amp;nbsp;intel's processor manual: link in section 8.2.3.4 it is stated that 
loads may not be &lt;/DIV&gt;
&lt;DIV&gt;reordered with earlier stores&amp;nbsp;to the same location, so lockfree_mpmc 
doesn't need &lt;/DIV&gt;
&lt;DIV&gt;and mfence between line [1] and [2] cause&amp;nbsp;there is a store and after that a 
load to &lt;/DIV&gt;
&lt;DIV&gt;the same location that is lastTail:.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;You can download lockfree_mpmc from:&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;A href="http://pages.videotron.com/aminer/"&gt;http://pages.videotron.com/aminer/&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Sincerely,&lt;/DIV&gt;
&lt;DIV&gt;Amine Moulay Ramdane.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;</description>
    <pubDate>Fri, 10 Aug 2012 16:13:56 GMT</pubDate>
    <dc:creator>aminer10</dc:creator>
    <dc:date>2012-08-10T16:13:56Z</dc:date>
    <item>
      <title>About lockfreE_mpmc .....</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/About-lockfreE-mpmc/m-p/769202#M105</link>
      <description>&lt;DIV&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;BR /&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;I wrote:&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&amp;gt; Hello all,&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; I think i have discovered a problem 
with lockfree_mpmc:&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; You will find the source code of 
lockfree_mpmc at:&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; &lt;A href="http://pages.videotron.com/aminer/"&gt;http://pages.videotron.com/aminer/&lt;/A&gt;&lt;BR /&gt;&amp;gt; 
&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; So please follow with me:&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; If you take a look 
at the lockfree_mpmc , here is&amp;nbsp; the source code&lt;BR /&gt;&amp;gt; of the push() 
method:&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; ---&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; function TLockfree_MPMC.push(tm : 
tNodeQueue):boolean;&lt;BR /&gt;&amp;gt; var lasttail,newtemp:long;&lt;BR /&gt;&amp;gt; 
i,j:integer;&lt;BR /&gt;&amp;gt; begin&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt;&amp;nbsp;if getlength &amp;gt;= fsize&lt;BR /&gt;&amp;gt;&amp;nbsp; 
then&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; begin&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; result:=false;&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
exit;&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; end;&lt;BR /&gt;&amp;gt; result:=true;&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; 
newTemp:=LockedIncLong(temp);&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; [1] lastTail:=newTemp-1;&lt;BR /&gt;&amp;gt; 
[2] setObject(lastTail,tm);&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; repeat&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt;&amp;nbsp;if 
CAS(tail,lasttail,newtemp)&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp; then&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; begin&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 
exit;&lt;BR /&gt;&amp;gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; end;&lt;BR /&gt;&amp;gt; sleep(0);&lt;BR /&gt;&amp;gt;&amp;nbsp;until false;&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; 
end;&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; ---&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; As you know in the x86 architecture 
Loads may be reordered with older stores&lt;BR /&gt;&amp;gt; to different locations.&lt;BR /&gt;&amp;gt; 
&lt;BR /&gt;&amp;gt; So in line [2] there is a load of tail and lasttail to the registers of 
the &lt;BR /&gt;&amp;gt; processor&lt;BR /&gt;&amp;gt; before calling setobject() and just before on 
line [1] there is a store to &lt;BR /&gt;&amp;gt; lasttail.&lt;BR /&gt;&amp;gt; &lt;BR /&gt;&amp;gt; So as you have 
noticed the processor can then reorder the loads on line [2] &lt;BR /&gt;&amp;gt; with the 
older&lt;BR /&gt;&amp;gt; store on line [1] and this will cause a problem, so i think i have 
to insert &lt;BR /&gt;&amp;gt; an mfence between&lt;BR /&gt;&amp;gt; line [1] and line [2].&lt;BR /&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;BR /&gt;In the&amp;nbsp;intel's processor manual: link in section 8.2.3.4 it is stated that 
loads may not be &lt;/DIV&gt;
&lt;DIV&gt;reordered with earlier stores&amp;nbsp;to the same location, so lockfree_mpmc 
doesn't need &lt;/DIV&gt;
&lt;DIV&gt;and mfence between line [1] and [2] cause&amp;nbsp;there is a store and after that a 
load to &lt;/DIV&gt;
&lt;DIV&gt;the same location that is lastTail:.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;You can download lockfree_mpmc from:&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;A href="http://pages.videotron.com/aminer/"&gt;http://pages.videotron.com/aminer/&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Sincerely,&lt;/DIV&gt;
&lt;DIV&gt;Amine Moulay Ramdane.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Fri, 10 Aug 2012 16:13:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/About-lockfreE-mpmc/m-p/769202#M105</guid>
      <dc:creator>aminer10</dc:creator>
      <dc:date>2012-08-10T16:13:56Z</dc:date>
    </item>
  </channel>
</rss>

