<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Ring 0 - CPU [0-3] - Stack segment in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Ring-0-CPU-0-3-Stack-segment/m-p/824031#M1334</link>
    <description>Each hardware thread would require a seperate stack.&lt;BR /&gt;&lt;BR /&gt;Note, the seperate stacks can be seperate areas within the same selector (with different esp/rsp) or within different selectors. This is an operating system design issue.&lt;BR /&gt;&lt;BR /&gt;Jim Dempsey&lt;BR /&gt;</description>
    <pubDate>Thu, 20 Jan 2011 23:40:03 GMT</pubDate>
    <dc:creator>jimdempseyatthecove</dc:creator>
    <dc:date>2011-01-20T23:40:03Z</dc:date>
    <item>
      <title>Ring 0 - CPU [0-3] - Stack segment</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Ring-0-CPU-0-3-Stack-segment/m-p/824030#M1333</link>
      <description>&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;When CPU switches from Ring-3 to Ring-0, SS is also switched to Ring-0 stack. In a multi-processor environment, if there are N number of CPU's, does each CPU will have it's own Ring-0 stack?&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Gupta&lt;/P&gt;</description>
      <pubDate>Thu, 13 Jan 2011 23:18:49 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Ring-0-CPU-0-3-Stack-segment/m-p/824030#M1333</guid>
      <dc:creator>mguptamel</dc:creator>
      <dc:date>2011-01-13T23:18:49Z</dc:date>
    </item>
    <item>
      <title>Ring 0 - CPU [0-3] - Stack segment</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Ring-0-CPU-0-3-Stack-segment/m-p/824031#M1334</link>
      <description>Each hardware thread would require a seperate stack.&lt;BR /&gt;&lt;BR /&gt;Note, the seperate stacks can be seperate areas within the same selector (with different esp/rsp) or within different selectors. This is an operating system design issue.&lt;BR /&gt;&lt;BR /&gt;Jim Dempsey&lt;BR /&gt;</description>
      <pubDate>Thu, 20 Jan 2011 23:40:03 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Ring-0-CPU-0-3-Stack-segment/m-p/824031#M1334</guid>
      <dc:creator>jimdempseyatthecove</dc:creator>
      <dc:date>2011-01-20T23:40:03Z</dc:date>
    </item>
  </channel>
</rss>

