https://community.intel.com/t5/Intel-Moderncode-for-Parallel/A-question-about-scalability-on-Nehalem-architecture/m-p/773398#M147 <BR />Hello, <BR /><BR /><BR />I was reading a paper about FC (flat combining) , and i came accross <BR />some graphs that shows the scalability on the Nehalem architecture: <BR /><BR /><BR />Here is the paper and the graphs in it: <BR /><BR /><BR /><A href="http://www.cs.tau.ac.il/research/moran.tzafrir/papers/spaa2010_flat_combining.pdf">http://www.cs.tau.ac.il/research/moran.tzafrir/papers/spaa2010_flat_combining.pdf</A><BR /><BR /><BR />As you will notice the Nehalem Intel architecture is giving a negative <BR />scalability for all the Queues, but on the SPARC architecture there is <BR />positive scalability.<BR /><BR />So my question is: <BR /><BR />Why all of the queues are giving a negative scalability on the Intel <BR />Nehalem architecture ? <BR /><BR />They are not saying on the paper why all the queues have a negative <BR />scalability .on the Intel Nehalem architecture.. <BR /><BR /><BR /><BR />thank you. <BR /><BR /><BR />Amine Moulay Ramdane. <BR /><BR /> Sat, 17 Dec 2011 18:02:19 GMT aminer10 2011-12-17T18:02:19Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/A-question-about-scalability-on-Nehalem-architecture/m-p/773398#M147 <BR />Hello, <BR /><BR /><BR />I was reading a paper about FC (flat combining) , and i came accross <BR />some graphs that shows the scalability on the Nehalem architecture: <BR /><BR /><BR />Here is the paper and the graphs in it: <BR /><BR /><BR /><A href="http://www.cs.tau.ac.il/research/moran.tzafrir/papers/spaa2010_flat_combining.pdf">http://www.cs.tau.ac.il/research/moran.tzafrir/papers/spaa2010_flat_combining.pdf</A><BR /><BR /><BR />As you will notice the Nehalem Intel architecture is giving a negative <BR />scalability for all the Queues, but on the SPARC architecture there is <BR />positive scalability.<BR /><BR />So my question is: <BR /><BR />Why all of the queues are giving a negative scalability on the Intel <BR />Nehalem architecture ? <BR /><BR />They are not saying on the paper why all the queues have a negative <BR />scalability .on the Intel Nehalem architecture.. <BR /><BR /><BR /><BR />thank you. <BR /><BR /><BR />Amine Moulay Ramdane. <BR /><BR /> Sat, 17 Dec 2011 18:02:19 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/A-question-about-scalability-on-Nehalem-architecture/m-p/773398#M147 aminer10 2011-12-17T18:02:19Z