<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic openMP bug in intel 11.1.064 ? in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/openMP-bug-in-intel-11-1-064/m-p/832494#M1557</link>
    <description>On IA32, Intel64 and AMD FLUSH(var)acts asa compiler directive&lt;BR /&gt;&lt;BR /&gt; if var is registered then&lt;BR /&gt; if register of var modified then&lt;BR /&gt; write to memory&lt;BR /&gt; end if&lt;BR /&gt; disassociate var from register&lt;BR /&gt; end if&lt;BR /&gt;&lt;BR /&gt;The write ordering should be preserved.&lt;BR /&gt;&lt;BR /&gt;Due to all checkvar being set and varified as .true. (indicated by all threads passing the test) this indicates that all threads passed through their slice of&lt;BR /&gt;&lt;BR /&gt; array(i) = iam+1&lt;BR /&gt; checkvar(i) = .true.&lt;BR /&gt;&lt;BR /&gt;and thus is indicitive of one or more of&lt;BR /&gt;&lt;BR /&gt;1) cache coherency system not correctly performing write combining&lt;BR /&gt; (I seriously doubt this would be true)&lt;BR /&gt;&lt;BR /&gt;2) the allocatable array isn't aligned to at least integer granularity&lt;BR /&gt;(I seriously doubt this would be true)&lt;BR /&gt;&lt;BR /&gt;3) compiler optimizations is batching up writes into larger GP register or SSE register then performing merge (read/modify/write) either at start of slice and/or end of slice&lt;BR /&gt;&lt;BR /&gt;4) bad code&lt;BR /&gt;&lt;BR /&gt;Can you produce an assembler listing then attach to reply to this forum?&lt;BR /&gt;&lt;BR /&gt;Jim Dempsey&lt;BR /&gt;</description>
    <pubDate>Sat, 30 Apr 2011 13:28:54 GMT</pubDate>
    <dc:creator>jimdempseyatthecove</dc:creator>
    <dc:date>2011-04-30T13:28:54Z</dc:date>
    <item>
      <title>openMP bug in intel 11.1.064 ?</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/openMP-bug-in-intel-11-1-064/m-p/832491#M1554</link>
      <description>&lt;DIV id="_mcePaste"&gt;&lt;DIV id="_mcePaste"&gt;Hi,&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;I experienced a problem (bug?) with the openMP code attached below. I tested the code on different architectures: dual socket quad core Intel Xeon E5450 and dual socket quad core AMD opteron experiencing the same problem.&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;I tried to be as simple as possible in the test code. I would write a code which guaranties me to safely enter to the last loop (see code) without issuing omp barriers. (...waiting for thread subteams in next versions of openMP...)&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;I use intel compiler and OMP_NUM_THREADS=8&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;[zorro@pordoi212 ~]$ ifort -V&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;Intel Fortran Intel 64 Compiler Professional for applications running on Intel 64, Version 11.1  Build 20100414 Package ID: l_cprof_p_11.1.072&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;Copyright (C) 1985-2010 Intel Corporation. All rights reserved.&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;When compiled without any other flag than -openmp, it doesn't provide the right answer (*)&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;DIV id="_mcePaste"&gt;[zorro@pordoi212 ~]$ ifort -openmp testflush.F90 -o tfint&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;[zorro@pordoi212 ~]$ ./tfint&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;Test (must be 0):      1&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;if I add -C flag (or -g), it works fine&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;&lt;DIV id="_mcePaste"&gt;[zorro@pordoi212 ~]$ ifort -openmp -g testflush.F90 -o tfint&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;[zorro@pordoi212 ~]$ ./tfint&lt;/DIV&gt;&lt;DIV id="_mcePaste"&gt;Test (must be 0):      0&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;[zorro@pordoi212 ~]$ ifort -openmp -C testflush.F90 -o tfint&lt;/DIV&gt;&lt;DIV&gt;[zorro@pordoi212 ~]$ ./tfint&lt;/DIV&gt;&lt;DIV&gt;Test (must be 0):      0&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;When compiling with pgi 10.3, the code is right (same with gcc)&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;[zorro@pordoi212 ~]$ pgf90 -mp testflush.F90 -o tfpgi&lt;/DIV&gt;&lt;DIV&gt;[zorro@pordoi212 ~]$ ./tfpgi&lt;/DIV&gt;&lt;DIV&gt;Test (must be 0):       0&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;If you compile on your environment, you can see that in the wrong case (*), listed times in fort.102 file reports that thread 2 (3 to 7 also in fort.103-107) doesn't wait for thread 1 completion (during checking loop)&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;times (write,loop) :  2.348423004150391E-004 9.536743164062500E-007&lt;/DIV&gt;&lt;DIV&gt;times (total)   :  2.357959747314453E-004&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;In other cases, reported times confirm the right behaviour (threads 2 to 7 wait for thread 1 completion), an example&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;times (write,loop) :  2.3508071899414062E-004  1.000094890594482&lt;/DIV&gt;&lt;DIV&gt;times (total)   :   1.000329971313477&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Some comments in the code add other details to the problem.&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;Regards,&lt;/DIV&gt;&lt;DIV&gt;Stefano&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;----------------Here is the code------------------------------------&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;program main&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;  implicit none&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;  include 'omp_lib.h'&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;  logical checkflag&lt;/DIV&gt;&lt;DIV&gt;  integer i,iam,arraysize,auxsl,nth,error,chunk,k&lt;/DIV&gt;&lt;DIV&gt;  double precision t(3)&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;  !logical, volatile, allocatable :: checkvarv(:) !same behaviour with volatile attribute&lt;/DIV&gt;&lt;DIV&gt;  logical, allocatable :: checkvarv(:)&lt;/DIV&gt;&lt;DIV&gt;  integer, allocatable :: array(:)&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;  arraysize=1000&lt;/DIV&gt;&lt;DIV&gt;  allocate(checkvarv(arraysize))&lt;/DIV&gt;&lt;DIV&gt;  checkvarv(:)=.false.&lt;/DIV&gt;&lt;DIV&gt;  allocate(array(arraysize))&lt;/DIV&gt;&lt;DIV&gt;  array=0&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;  error=0&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;!$omp parallel default(none) shared(error,arraysize,nth,checkvarv,array) private(iam,checkflag,auxsl,t,i,k)&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;  iam=OMP_GET_THREAD_NUM()&lt;/DIV&gt;&lt;DIV&gt;  auxsl=0&lt;/DIV&gt;&lt;DIV&gt;  checkflag=.false.&lt;/DIV&gt;&lt;DIV&gt;!$omp single&lt;/DIV&gt;&lt;DIV&gt;  nth=OMP_GET_NUM_THREADS()&lt;/DIV&gt;&lt;DIV&gt;!$omp end single&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;  t(1)=OMP_GET_WTIME()&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;! Thread 0 performs some MPI operation....&lt;/DIV&gt;&lt;DIV&gt;  if(iam.eq.0) call sleep(2)&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;! Misalign thread 1 with respect to other threads when writing to array&lt;/DIV&gt;&lt;DIV&gt;!$omp do schedule(dynamic,1)&lt;/DIV&gt;&lt;DIV&gt;  do i=1,arraysize&lt;/DIV&gt;&lt;DIV&gt;   if(iam.eq.1.and.auxsl.eq.0) then&lt;/DIV&gt;&lt;DIV&gt;    auxsl=1&lt;/DIV&gt;&lt;DIV&gt;    call sleep(1)&lt;/DIV&gt;&lt;DIV&gt;   endif&lt;/DIV&gt;&lt;DIV&gt;   array(i)=iam+1&lt;/DIV&gt;&lt;DIV&gt;   checkvarv(i)=.true.&lt;/DIV&gt;&lt;DIV&gt;  enddo&lt;/DIV&gt;&lt;DIV&gt;!$omp end do nowait&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;  t(2)=OMP_GET_WTIME()&lt;/DIV&gt;&lt;DIV&gt;! Loops until previous write loop is finished&lt;/DIV&gt;&lt;DIV&gt;  do while(.not.checkflag)&lt;/DIV&gt;&lt;DIV&gt;!!$omp flush(checkvarv) ! if you uncomment this line, you obtain the right answer with -openmp flag only.&lt;/DIV&gt;&lt;DIV&gt;   checkflag=.true.&lt;/DIV&gt;&lt;DIV&gt;   do k=1,arraysize&lt;/DIV&gt;&lt;DIV&gt;    checkflag = (checkflag.and.checkvarv(k))&lt;/DIV&gt;&lt;DIV&gt;   end do&lt;/DIV&gt;&lt;DIV&gt;  end do&lt;/DIV&gt;&lt;DIV&gt;  t(3)=OMP_GET_WTIME()&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;! Can we enter this loop safely?&lt;/DIV&gt;&lt;DIV&gt;!$omp do schedule(dynamic,1)&lt;/DIV&gt;&lt;DIV&gt;  do i=1,arraysize&lt;/DIV&gt;&lt;DIV&gt;   if(array(i).eq.0) error=1&lt;/DIV&gt;&lt;DIV&gt;  enddo&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;!$omp end do nowait&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;  write(100+iam,*) 'times (write,loop) : ',t(2)-t(1),t(3)-t(2)&lt;/DIV&gt;&lt;DIV&gt;  write(100+iam,*) 'times (total)   : ',t(3)-t(1)&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;!$omp end parallel&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;  write(*,*) "Test (must be 0): ",error&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;  write(200,*) array-1&lt;/DIV&gt;&lt;DIV&gt;  deallocate(array)&lt;/DIV&gt;&lt;DIV&gt;  deallocate(checkvarv)&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;end&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;--------------------------------------------------------------------------------&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Thu, 28 Apr 2011 10:55:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/openMP-bug-in-intel-11-1-064/m-p/832491#M1554</guid>
      <dc:creator>stefanoz</dc:creator>
      <dc:date>2011-04-28T10:55:08Z</dc:date>
    </item>
    <item>
      <title>openMP bug in intel 11.1.064 ?</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/openMP-bug-in-intel-11-1-064/m-p/832492#M1555</link>
      <description>Try inserting:&lt;BR /&gt;&lt;BR /&gt; !$omp flush(array)&lt;BR /&gt;&lt;BR /&gt;after&lt;BR /&gt;&lt;BR /&gt; ! Can we enter this loop safely&lt;BR /&gt;&lt;BR /&gt;However, instead consider placing&lt;BR /&gt;&lt;BR /&gt; !$omp flush(array)&lt;BR /&gt; !$omp flush(checkvarg)&lt;BR /&gt;&lt;BR /&gt;immediately after the&lt;BR /&gt;&lt;BR /&gt; !$omp end do nowait&lt;BR /&gt;&lt;BR /&gt;that fills in the array.&lt;BR /&gt;&lt;BR /&gt;N.B. I specified two seperate flush(..) in hope that the flushes occur as sequenced. Placing both variables(arrays) in the same statement is ambiguous to order. IA36/Intel64 should preserve write ordering however the compiler optimizations might resequence instructions and/or use streaming writes and/or write merging. To check for these conditions, examine the results of your&lt;BR /&gt;&lt;BR /&gt; &lt;SPAN style="font-size: x-small;"&gt;&lt;FONT size="2"&gt;&lt;P&gt;&lt;/P&gt;&lt;/FONT&gt;&lt;/SPAN&gt;&lt;P&gt;&lt;B&gt;&lt;SPAN style="color: #0000ff; font-size: x-small;"&gt;&lt;SPAN style="color: #0000ff; font-size: x-small;"&gt;write&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/B&gt;&lt;SPAN style="font-size: x-small;"&gt;(200,*) array-1&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;BR /&gt;If you see any -1's then a write was not issued or bunged up with SSE merge (read, modify (with mask), write).&lt;BR /&gt;If you see all 0:nth-1's then the issue is with the flush.&lt;BR /&gt;&lt;BR /&gt;Jim Dempsey&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Fri, 29 Apr 2011 15:53:56 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/openMP-bug-in-intel-11-1-064/m-p/832492#M1555</guid>
      <dc:creator>jimdempseyatthecove</dc:creator>
      <dc:date>2011-04-29T15:53:56Z</dc:date>
    </item>
    <item>
      <title>openMP bug in intel 11.1.064 ?</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/openMP-bug-in-intel-11-1-064/m-p/832493#M1556</link>
      <description>Your suggestions doesn't work. I put also them together in the code but it gives me the wrong output. I think the issue is with flush.</description>
      <pubDate>Sat, 30 Apr 2011 08:42:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/openMP-bug-in-intel-11-1-064/m-p/832493#M1556</guid>
      <dc:creator>stefanoz</dc:creator>
      <dc:date>2011-04-30T08:42:52Z</dc:date>
    </item>
    <item>
      <title>openMP bug in intel 11.1.064 ?</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/openMP-bug-in-intel-11-1-064/m-p/832494#M1557</link>
      <description>On IA32, Intel64 and AMD FLUSH(var)acts asa compiler directive&lt;BR /&gt;&lt;BR /&gt; if var is registered then&lt;BR /&gt; if register of var modified then&lt;BR /&gt; write to memory&lt;BR /&gt; end if&lt;BR /&gt; disassociate var from register&lt;BR /&gt; end if&lt;BR /&gt;&lt;BR /&gt;The write ordering should be preserved.&lt;BR /&gt;&lt;BR /&gt;Due to all checkvar being set and varified as .true. (indicated by all threads passing the test) this indicates that all threads passed through their slice of&lt;BR /&gt;&lt;BR /&gt; array(i) = iam+1&lt;BR /&gt; checkvar(i) = .true.&lt;BR /&gt;&lt;BR /&gt;and thus is indicitive of one or more of&lt;BR /&gt;&lt;BR /&gt;1) cache coherency system not correctly performing write combining&lt;BR /&gt; (I seriously doubt this would be true)&lt;BR /&gt;&lt;BR /&gt;2) the allocatable array isn't aligned to at least integer granularity&lt;BR /&gt;(I seriously doubt this would be true)&lt;BR /&gt;&lt;BR /&gt;3) compiler optimizations is batching up writes into larger GP register or SSE register then performing merge (read/modify/write) either at start of slice and/or end of slice&lt;BR /&gt;&lt;BR /&gt;4) bad code&lt;BR /&gt;&lt;BR /&gt;Can you produce an assembler listing then attach to reply to this forum?&lt;BR /&gt;&lt;BR /&gt;Jim Dempsey&lt;BR /&gt;</description>
      <pubDate>Sat, 30 Apr 2011 13:28:54 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/openMP-bug-in-intel-11-1-064/m-p/832494#M1557</guid>
      <dc:creator>jimdempseyatthecove</dc:creator>
      <dc:date>2011-04-30T13:28:54Z</dc:date>
    </item>
    <item>
      <title>openMP bug in intel 11.1.064 ?</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/openMP-bug-in-intel-11-1-064/m-p/832495#M1558</link>
      <description>Stefano,&lt;BR /&gt;&lt;BR /&gt;Thanks for the assembly listings. I haven't investigated thoroughly (I'm not from Intel) but I see some flow control problems with your testflush1.s listing. Assuming this was generated from your first message then we see:&lt;BR /&gt;&lt;BR /&gt;&lt;PRE&gt;[cpp]..B1.56:                        # Preds ..B1.44 ..B1.50
        xorl      %eax, %eax                                    #52.12
        call      omp_get_wtime_                                #52.12
                                # LOE r13 r12d r14d xmm0
..B1.131:                       # Preds ..B1.56
        movsd     %xmm0, -128(%rbp)                             #52.12
                                # LOE r13 r12d r14d
..B1.57:                        # Preds ..B1.131
        xorl      %eax, %eax                                    #61.12
        call      omp_get_wtime_                                #61.12
                                # LOE r13 r12d r14d xmm0
..B1.132:                       # Preds ..B1.57
        movsd     %xmm0, -104(%rbp)                             #61.12
[/cpp]&lt;/PRE&gt;&lt;BR /&gt;Two of the omp_get_wtime_ function calls are made back-to-back with no interviening code.&lt;BR /&gt;Meaning this code section did not follow the sequence of operations (or equivilent to the sequence of operations)in the original source code.&lt;BR /&gt;&lt;BR /&gt;The write loop for filling in the array and chedkvar values was sequenced properly.&lt;BR /&gt;&lt;BR /&gt;If the code flow for the code around (between) your loops is incorrect then it is possible that you could incorrectly sequence the test for array fill done.&lt;BR /&gt;&lt;BR /&gt;Again, I wish to state I did not examine the code flow further than the first error.&lt;BR /&gt;&lt;BR /&gt;Additional note:&lt;BR /&gt;&lt;BR /&gt;The two omp_get_wtime_ function calls above store into&lt;BR /&gt;&lt;BR /&gt; -128(%rbp) and -104(%rbp)&lt;BR /&gt;&lt;BR /&gt;the third call stores into -112(%rbp)&lt;BR /&gt;&lt;BR /&gt;These three stores are to corrolat to&lt;BR /&gt;&lt;BR /&gt; double precision t(3)&lt;BR /&gt;&lt;BR /&gt;The above array should encompass 3 * real(8)&lt;BR /&gt;&lt;BR /&gt;If -128(%rbp) is t(1), then t(2) should be -120(%rbp), t(3) should be -112(%rbp), t(4) at -104(%rbp)&lt;BR /&gt;IOW the array addresses for t are messed up. Now the compiler optimizations could determine that array t is only unsed within this program and each cell referenced is unique (i.e. not passing t(1:3) outside the program), and then take the liberty to move the data around, however the debugger would have a problem in displaying the discontiguous array t.&lt;BR /&gt;&lt;BR /&gt;Jim Dempsey&lt;BR /&gt;</description>
      <pubDate>Mon, 02 May 2011 13:19:15 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/openMP-bug-in-intel-11-1-064/m-p/832495#M1558</guid>
      <dc:creator>jimdempseyatthecove</dc:creator>
      <dc:date>2011-05-02T13:19:15Z</dc:date>
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