https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Causal-Consistency/m-p/834719#M1593 Hi<DIV>(Vol 3A -8.2.3.6) "Stores are Transitively Visible"</DIV><DIV></DIV><DIV>Two thoughts:</DIV><DIV><A> <MINOR nit=""> shouldnt code for Processor 1 be</MINOR></A></DIV><DIV>+ mov [_y], r1</DIV><DIV>- mov [_y], 1 &lt;&lt;&lt;&lt; with a constant write of 1 to y theres no causal relationship?</DIV><DIV></DIV><DIV><B> more importantly... does causal relation include control dependencies. (A = B = 0)</B></DIV><DIV>P0: A = 1</DIV><DIV></DIV><DIV>P1: while(A != 1){}</DIV><DIV> B = 2</DIV><DIV></DIV><DIV>P2: while (B != 2){}</DIV><DIV> print(A)</DIV><DIV></DIV><DIV>Are the 2 writes A = 1 and B = 2 causally related?</DIV><DIV></DIV><DIV>Regards</DIV><DIV>banks</DIV><DIV></DIV> Sun, 24 Apr 2011 23:04:34 GMT bank_kus 2011-04-24T23:04:34Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Causal-Consistency/m-p/834719#M1593 Hi<DIV>(Vol 3A -8.2.3.6) "Stores are Transitively Visible"</DIV><DIV></DIV><DIV>Two thoughts:</DIV><DIV><A> <MINOR nit=""> shouldnt code for Processor 1 be</MINOR></A></DIV><DIV>+ mov [_y], r1</DIV><DIV>- mov [_y], 1 &lt;&lt;&lt;&lt; with a constant write of 1 to y theres no causal relationship?</DIV><DIV></DIV><DIV><B> more importantly... does causal relation include control dependencies. (A = B = 0)</B></DIV><DIV>P0: A = 1</DIV><DIV></DIV><DIV>P1: while(A != 1){}</DIV><DIV> B = 2</DIV><DIV></DIV><DIV>P2: while (B != 2){}</DIV><DIV> print(A)</DIV><DIV></DIV><DIV>Are the 2 writes A = 1 and B = 2 causally related?</DIV><DIV></DIV><DIV>Regards</DIV><DIV>banks</DIV><DIV></DIV> Sun, 24 Apr 2011 23:04:34 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Causal-Consistency/m-p/834719#M1593 bank_kus 2011-04-24T23:04:34Z