<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic miss cache in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/miss-cache/m-p/838497#M1637</link>
    <description>Hi,&lt;BR /&gt;i still surprised with the result that i obtained when i runned the microbenchmark to detect the L1 and L2 miss caches for double type in multiplication matrix program. The L2 miss started in at a &lt;B&gt;value of number of memory access&lt;/B&gt; upper (very &amp;gt;&amp;gt;)than the L1 miss one. And wich is more weird is that this value of L2 miss is upper than the miss L2 value of the type integer.Is it logical to obtain this!&lt;BR /&gt;My processor is intel  core2duo cpuT7500 @2.2Ghz&lt;BR /&gt;Please help me!!!!!!!!!!!!!!!!!!!!!!!!!!!&lt;BR /&gt;Thanks a lot.</description>
    <pubDate>Thu, 15 Apr 2010 18:31:08 GMT</pubDate>
    <dc:creator>sammoura</dc:creator>
    <dc:date>2010-04-15T18:31:08Z</dc:date>
    <item>
      <title>miss cache</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/miss-cache/m-p/838497#M1637</link>
      <description>Hi,&lt;BR /&gt;i still surprised with the result that i obtained when i runned the microbenchmark to detect the L1 and L2 miss caches for double type in multiplication matrix program. The L2 miss started in at a &lt;B&gt;value of number of memory access&lt;/B&gt; upper (very &amp;gt;&amp;gt;)than the L1 miss one. And wich is more weird is that this value of L2 miss is upper than the miss L2 value of the type integer.Is it logical to obtain this!&lt;BR /&gt;My processor is intel  core2duo cpuT7500 @2.2Ghz&lt;BR /&gt;Please help me!!!!!!!!!!!!!!!!!!!!!!!!!!!&lt;BR /&gt;Thanks a lot.</description>
      <pubDate>Thu, 15 Apr 2010 18:31:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/miss-cache/m-p/838497#M1637</guid>
      <dc:creator>sammoura</dc:creator>
      <dc:date>2010-04-15T18:31:08Z</dc:date>
    </item>
  </channel>
</rss>

