topic Atomicity of load operation on ia64 in Intel® Moderncode for Parallel Architectures

Atomicity of load operation on ia64

ggalperin — Fri, 30 Jan 2009 15:58:07 GMT

Is it guaranteed on ia64 architecture in multi-processor environment that a plain load operation would fetch a 64-bit value atomically? In other words, is it possible that if CPU1 stores some value to a 64-bit memory location and CPU2 fetches the value from the same memory location at the same time, the fetched value would be neither one before nor after store operation?
Thx, ---Greg

Re: Atomicity of load operation on ia64

TimP — Sat, 31 Jan 2009 02:46:26 GMT

64-bit int load on 64-bit architectures is definitely an atomic operation, unlike 32-bit x86, where it is done by a pair of 32-bit loads.

Re: Atomicity of load operation on ia64

Dmitry_Vyukov — Sat, 31 Jan 2009 12:41:36 GMT

Quoting - ggalperin

8-, 16-, 32-, 64-, 128-bit aligned loads and stores are indeed atomic on IA-64.
However to get them you probably have to use something like SSE intrinsics or assembly.

For details see:
Intel Itanium Architecture Software Developer's Manual - Volume 2: System Architecture, Revision 2.2
http://www.intel.com/design/itanium/manuals/245318.htm
(4.5 Memory Datum Alignment and Atomicity)

Re: Atomicity of load operation on ia64

Dmitry_Vyukov — Sat, 31 Jan 2009 13:09:54 GMT

Quoting - Dmitriy Vyukov

Hmmm... Do you sure that you mean exactly IA-64 (i.e. Itanium)? Probably you mean Intel 64 (i.e. x86-64)...
However, 8-, 16-, 32-, 64-, 128-bit aligned loads and stores are also atomic on IA-32 (i.e. x86) and on Intel 64 (i.e. x86-64). But don't try to extend this to the C language, for example. In order to get 128-bit atomic load/store you have to emit some particular machine instruction, not just plain access to 128-bit variable in the C source.

Re: Atomicity of load operation on ia64

ggalperin — Sun, 01 Feb 2009 04:04:56 GMT

Quoting - Dmitriy Vyukov

Yes, I meant ia64 (Itanium). Thanks for the details. Will definitely use asm instructions and align data properly.
Just want to clarify: even if a 64-bit word is only 8-bit aligned, I can still emit a certain atomic load/store instruction on Itanium that will be atomic? Thx.

Re: Atomicity of load operation on ia64

TimP — Sun, 01 Feb 2009 06:37:57 GMT

Quoting - ggalperin

even if a 64-bit word is only 8-bit aligned, I can still emit a certain atomic load/store instruction on Itanium that will be atomic?

On IA64. 64-bit memory access has to be 64-bit aligned in order to be performed by a single instruction. Unaligned access will abort the application, unless it is done by several smaller width instructions. It makes no difference whether asm is used for the load alone, compilers don't provide for unaligned loads. If you have a BIOS option set to retry unaligned memory access, that is very slow, and not atomic.
For load-update-store, you have several options, including OpenMP atomic.