https://community.intel.com/t5/Intel-Moderncode-for-Parallel/xeon-quad-core/m-p/854210#M2010 <DIV style="margin:0px;"> <DIV id="quote_reply" style="width: 100%; margin-top: 5px;"> <DIV style="margin-left:2px;margin-right:2px;">Quoting - <A href="https://community.intel.com/en-us/profile/425204">boriwalanirmal</A></DIV> <DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"><EM>in Xeon quad core 2 cores share l2. but does shared l2 shareport to cores </EM></DIV> </DIV> </DIV> I'm not sure what you're getting at here. In the Core 2 quad, each pair of cores communicated through their L1 cache pair to the shared L2. There was no on-chip direct path between the L2 caches.<BR /> Wed, 22 Apr 2009 02:02:32 GMT TimP 2009-04-22T02:02:32Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/xeon-quad-core/m-p/854209#M2009 in Xeon quad core 2 cores share l2. but does shared l2 shareport to cores Tue, 21 Apr 2009 19:11:56 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/xeon-quad-core/m-p/854209#M2009 boriwalanirmal 2009-04-21T19:11:56Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/xeon-quad-core/m-p/854210#M2010 <DIV style="margin:0px;"> <DIV id="quote_reply" style="width: 100%; margin-top: 5px;"> <DIV style="margin-left:2px;margin-right:2px;">Quoting - <A href="https://community.intel.com/en-us/profile/425204">boriwalanirmal</A></DIV> <DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"><EM>in Xeon quad core 2 cores share l2. but does shared l2 shareport to cores </EM></DIV> </DIV> </DIV> I'm not sure what you're getting at here. In the Core 2 quad, each pair of cores communicated through their L1 cache pair to the shared L2. There was no on-chip direct path between the L2 caches.<BR /> Wed, 22 Apr 2009 02:02:32 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/xeon-quad-core/m-p/854210#M2010 TimP 2009-04-22T02:02:32Z