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    <title>topic Re: L1 and L2 latency in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/L1-and-L2-latency/m-p/856247#M2098</link>
    <description>I think I have what you need: &lt;A href="http://www.xbitlabs.com/articles/mobile/print/core2duo.html"&gt;http://www.xbitlabs.com/articles/mobile/print/core2duo.html&lt;/A&gt;.&lt;BR /&gt;Scroll down a bit, you will find a table. The Merom column (T5500 is from the Merom family) is what you are looking for.&lt;BR /&gt;</description>
    <pubDate>Tue, 14 Jul 2009 14:01:45 GMT</pubDate>
    <dc:creator>Tudor</dc:creator>
    <dc:date>2009-07-14T14:01:45Z</dc:date>
    <item>
      <title>L1 and L2 latency</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/L1-and-L2-latency/m-p/856244#M2095</link>
      <description>hi all&lt;BR /&gt;in my performance model witch i develloped i need to introduce L1 and L2 latency of my processor (intel core 2 duo T5500)&lt;BR /&gt;but i dont knew where can we find this information&lt;BR /&gt;thanks a lot</description>
      <pubDate>Tue, 14 Jul 2009 10:58:21 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/L1-and-L2-latency/m-p/856244#M2095</guid>
      <dc:creator>karimfath</dc:creator>
      <dc:date>2009-07-14T10:58:21Z</dc:date>
    </item>
    <item>
      <title>Re: L1 and L2 latency</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/L1-and-L2-latency/m-p/856245#M2096</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
Here is something you might find useful: &lt;A href="http://www.adriansrojakpot.com/Speed_Demonz/L2_Cache_Latency/L2_Cache_Latency_02.htm"&gt;http://www.adriansrojakpot.com/Speed_Demonz/L2_Cache_Latency/L2_Cache_Latency_02.htm&lt;/A&gt;. Dunno if your bios has that option.&lt;BR /&gt;</description>
      <pubDate>Tue, 14 Jul 2009 11:07:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/L1-and-L2-latency/m-p/856245#M2096</guid>
      <dc:creator>Tudor</dc:creator>
      <dc:date>2009-07-14T11:07:45Z</dc:date>
    </item>
    <item>
      <title>Re: L1 and L2 latency</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/L1-and-L2-latency/m-p/856246#M2097</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/435330"&gt;Tudor Serban&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt; Here is something you might find useful: &lt;A href="http://www.adriansrojakpot.com/Speed_Demonz/L2_Cache_Latency/L2_Cache_Latency_02.htm"&gt;http://www.adriansrojakpot.com/Speed_Demonz/L2_Cache_Latency/L2_Cache_Latency_02.htm&lt;/A&gt;. Dunno if your bios has that option.&lt;BR /&gt;&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
thanks tudor but we dont find this option in my bios and this method cant give me the L1 latency&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Tue, 14 Jul 2009 11:58:46 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/L1-and-L2-latency/m-p/856246#M2097</guid>
      <dc:creator>karimfath</dc:creator>
      <dc:date>2009-07-14T11:58:46Z</dc:date>
    </item>
    <item>
      <title>Re: L1 and L2 latency</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/L1-and-L2-latency/m-p/856247#M2098</link>
      <description>I think I have what you need: &lt;A href="http://www.xbitlabs.com/articles/mobile/print/core2duo.html"&gt;http://www.xbitlabs.com/articles/mobile/print/core2duo.html&lt;/A&gt;.&lt;BR /&gt;Scroll down a bit, you will find a table. The Merom column (T5500 is from the Merom family) is what you are looking for.&lt;BR /&gt;</description>
      <pubDate>Tue, 14 Jul 2009 14:01:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/L1-and-L2-latency/m-p/856247#M2098</guid>
      <dc:creator>Tudor</dc:creator>
      <dc:date>2009-07-14T14:01:45Z</dc:date>
    </item>
    <item>
      <title>Re: L1 and L2 latency</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/L1-and-L2-latency/m-p/856248#M2099</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/435330"&gt;Tudor Serban&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;I think I have what you need: &lt;A href="http://www.xbitlabs.com/articles/mobile/print/core2duo.html"&gt;http://www.xbitlabs.com/articles/mobile/print/core2duo.html&lt;/A&gt;.&lt;BR /&gt;Scroll down a bit, you will find a table. The Merom column (T5500 is from the Merom family) is what you are looking for.&lt;BR /&gt;&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
thanks a lot my freind this is realy what we want &lt;BR /&gt;</description>
      <pubDate>Wed, 15 Jul 2009 14:00:34 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/L1-and-L2-latency/m-p/856248#M2099</guid>
      <dc:creator>karimfath</dc:creator>
      <dc:date>2009-07-15T14:00:34Z</dc:date>
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