<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic How to implement HW-thread private memory in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-implement-HW-thread-private-memory/m-p/856532#M2124</link>
    <description>Let's say I have a pointer char *p. How can I implement behavior, in which depending on which processor is doing pointer dereference, different data is accessed?&lt;BR /&gt;&lt;BR /&gt;I want something like Thread Local Storage, but for HW thread (something like HW-thread Local Storage, CPU Local Storage).&lt;BR /&gt;&lt;BR /&gt;char *p = ...; // Initialization should be done in some special way, probably&lt;BR /&gt;char *local_p = get_hwls(p);&lt;BR /&gt;</description>
    <pubDate>Thu, 01 Oct 2009 15:56:12 GMT</pubDate>
    <dc:creator>gallus2</dc:creator>
    <dc:date>2009-10-01T15:56:12Z</dc:date>
    <item>
      <title>How to implement HW-thread private memory</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-implement-HW-thread-private-memory/m-p/856532#M2124</link>
      <description>Let's say I have a pointer char *p. How can I implement behavior, in which depending on which processor is doing pointer dereference, different data is accessed?&lt;BR /&gt;&lt;BR /&gt;I want something like Thread Local Storage, but for HW thread (something like HW-thread Local Storage, CPU Local Storage).&lt;BR /&gt;&lt;BR /&gt;char *p = ...; // Initialization should be done in some special way, probably&lt;BR /&gt;char *local_p = get_hwls(p);&lt;BR /&gt;</description>
      <pubDate>Thu, 01 Oct 2009 15:56:12 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-implement-HW-thread-private-memory/m-p/856532#M2124</guid>
      <dc:creator>gallus2</dc:creator>
      <dc:date>2009-10-01T15:56:12Z</dc:date>
    </item>
    <item>
      <title>Re: How to implement HW-thread private memory</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-implement-HW-thread-private-memory/m-p/856533#M2125</link>
      <description>&lt;DIV style="margin:0px;"&gt;&lt;/DIV&gt;
Maybe one of us is missing a point. As tls would be associated with a software thread, hardware affinity would associate both the thread and the tls sufficiently closely with hardware cache and local RAM to give the performance benefits.&lt;BR /&gt;</description>
      <pubDate>Thu, 01 Oct 2009 17:40:03 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-implement-HW-thread-private-memory/m-p/856533#M2125</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2009-10-01T17:40:03Z</dc:date>
    </item>
    <item>
      <title>Re: How to implement HW-thread private memory</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-implement-HW-thread-private-memory/m-p/856534#M2126</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/367365"&gt;tim18&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt; Maybe one of us is missing a point. As tls would be associated with a software thread, hardware affinity would associate both the thread and the tls sufficiently closely with hardware cache and local RAM to give the performance benefits.&lt;BR /&gt;&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;Indeed. Also, if the software thread is not tied to a particular hardware thread then the code would be pretty meaningless: the hardware thread used to set or retrieve the value could in principle be distinct to that used to run the code immediately before and after the value was accessed.&lt;BR /&gt;</description>
      <pubDate>Thu, 01 Oct 2009 20:28:40 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-implement-HW-thread-private-memory/m-p/856534#M2126</guid>
      <dc:creator>anthony_williams</dc:creator>
      <dc:date>2009-10-01T20:28:40Z</dc:date>
    </item>
    <item>
      <title>Re: How to implement HW-thread private memory</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-implement-HW-thread-private-memory/m-p/856535#M2127</link>
      <description>&lt;DIV style="margin:0px;"&gt;&lt;/DIV&gt;
&lt;BR /&gt;The only HW local storage you have is/are the registers (IA). And depending on your scoping interpretation, this might extend into L1, L2, L3 cache.&lt;BR /&gt;&lt;BR /&gt;When using O/S calls for restricting the affinity of a software thread to a HW thread you can have some measure of selection for the cache storage</description>
      <pubDate>Thu, 01 Oct 2009 22:06:39 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-implement-HW-thread-private-memory/m-p/856535#M2127</guid>
      <dc:creator>jimdempseyatthecove</dc:creator>
      <dc:date>2009-10-01T22:06:39Z</dc:date>
    </item>
  </channel>
</rss>

