topic atomic accesses in Intel® Moderncode for Parallel Architectures https://community.intel.com/t5/Intel-Moderncode-for-Parallel/atomic-accesses/m-p/870545#M2885 System Programming Guide 3A says: <DIV><BR /></DIV> <DIV>Section 7.1.1<BR />&gt;&gt; Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within a cache line</DIV> <DIV><BR /></DIV> <DIV>Does this really mean "cached memory" or is the intent here "cacheable memory", as if it is intended to be cached memory then it does not give much to application programmers, does it?</DIV> <DIV><BR /></DIV> <DIV><BR /></DIV> <DIV><BR /></DIV> Thu, 03 Dec 2009 20:01:24 GMT _ace_ 2009-12-03T20:01:24Z atomic accesses https://community.intel.com/t5/Intel-Moderncode-for-Parallel/atomic-accesses/m-p/870545#M2885 System Programming Guide 3A says: <DIV><BR /></DIV> <DIV>Section 7.1.1<BR />&gt;&gt; Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within a cache line</DIV> <DIV><BR /></DIV> <DIV>Does this really mean "cached memory" or is the intent here "cacheable memory", as if it is intended to be cached memory then it does not give much to application programmers, does it?</DIV> <DIV><BR /></DIV> <DIV><BR /></DIV> <DIV><BR /></DIV> Thu, 03 Dec 2009 20:01:24 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/atomic-accesses/m-p/870545#M2885 _ace_ 2009-12-03T20:01:24Z