topic Support for C/C++0x atomic operations in Intel® Moderncode for Parallel Architectures

Support for C/C++0x atomic operations

Dmitry_Vyukov — Tue, 30 Sep 2008 05:08:27 GMT

Does Intel have some plans to support "fine-grained" atomic operations in future x86 processors in the context of emerging C/C++0x standard and it's support for such operations?

Particularly I mean atomic RMW operations (XADD, XCHG, CMPXCHG, ADD, AND etc) with fine-grained memory ordering parameters. For example:

std::atomic_xchg(x, 1, std::memory_order_relaxed);

or:

std::atomic_fetch_sub(x, 1, std::memory_order_release);

The main point is that programs relying on C/C++0x atomic API will be able to transparently benefit from those fine-grained hardware operations.

Since load on x86 is always acquire, and store is always release, so I think it will be difficult to eliminate acquire/release fences, i.e. provide real relaxed operations. But at least store-load memory fence can be eliminated from atomic RMW operations. Is it possible/feasible?

Re: Support for C/C++0x atomic operations

AaronTersteeg — Thu, 12 Nov 2009 23:04:29 GMT

Quoting - Dmitriy Vyukov

Dmitriy,

Intel generally does not comment on future architectures but we have announced Intel AVX. There is a good overview paper on the new instructions and capabilities.

http://software.intel.com/en-us/articles/intel-avx-new-frontiers-in-performance-improvements-and-energy-efficiency

Cheers,

Aaron

Re: Support for C/C++0x atomic operations

Dmitry_Vyukov — Thu, 12 Nov 2009 23:17:26 GMT

As far as I understand it's not quite what I was talking about.