topic Inclusion Property in Multilevel Caches in Intel® Moderncode for Parallel Architectures

Inclusion Property in Multilevel Caches

anilkatti — Sat, 20 Feb 2010 19:16:55 GMT

Hi All,

I am working on inclusion property in multilevel cache systems. Can anyone of you tell me if Intel ensures inclusion property at every level of cache in their multicore architecture?

What does intel processors use for ensuring cache coherency? Snooping or invalidation techniques? I appreciate any type of help on these..

Thanks,

Anil.

Inclusion Property in Multilevel Caches

TimP — Sun, 21 Feb 2010 15:21:53 GMT

There are examples of all of these techniques. I don't know that this fairly broad subject is covered authoritatively in any more accessible document than the architecture manuals.

Inclusion Property in Multilevel Caches

anilkatti — Sun, 21 Feb 2010 18:43:59 GMT

Hi tim18,

Thanks for your reply. Did you mean, if these topics are covered they should in architecture manuals?

- Anil.

Inclusion Property in Multilevel Caches

anilkatti — Mon, 22 Feb 2010 15:26:24 GMT

Robert Said, "Any implementation insights? The last level cache is inclusive: if a cache line lives in L1 or L2 on one of the cores, it will also have a place in the L3and yes, it helps to reduce snoop traffic. But not eliminate it--still need snoops from L3 if you've got multiple sockets. But, we are getting far afield from the topic of this thread. If you want to continue with these questions,I think you should start a thread with a more appropriate title."

Yes, I understand what inclusion means. I wanted it's actual implementation details. In the sense - do they use an inclusion bit too keep track of all the cache lines existing in lower level caches? Or is there some other efficient technique?

Great! L3 snoops to see if some other processor writes to the memory. Makes sense. By any chance, can a I/O write to a memory location which can be cacheable?

Thanks,

Anil.

Inclusion Property in Multilevel Caches

robert-reed — Mon, 22 Feb 2010 20:09:52 GMT

I hate to RTFM you, but the aforementioned architecture manuals that Tim referred to and to which I provided you a link on the other thread should have some information on I/O and cacheable memory. I don't think the SPG gets into implementation details on L3 inclusion. I'd search the architecture journals and conferences to see if anything has been published. I don't know of anything.

Inclusion Property in Multilevel Caches

anilkatti — Mon, 22 Feb 2010 20:13:35 GMT

Thanks for that Robert~

- Anil.