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    <title>topic fazing out x86, simple solution in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/fazing-out-x86-simple-solution/m-p/887890#M3639</link>
    <description>Hi,&lt;BR /&gt;&lt;BR /&gt;I am a ComputerScience student, and I had an idea that I didn't know where to post. But thankfully to Lexi S. from Intel Software Network Support guided me to post it here.&lt;BR /&gt;&lt;BR /&gt;It seems I can't attach a PDF, so I copied the text. &lt;BR /&gt;&lt;BR /&gt;Me and my friend would be greatefull for any comment/remark on this idea sketch.&lt;BR /&gt;&lt;BR /&gt;------------------------------------------------------------------&lt;BR /&gt;


	
	
	
	

&lt;P align="left"&gt;&lt;U&gt;&lt;B&gt;Abstract:&lt;/B&gt;&lt;/U&gt;&lt;SPAN&gt;&lt;SPAN&gt;
Today everyone asks the question about what are we going to do with
quad or even octal cores? Maybe we can put in a GPU, sound card or
other cool things. But all this comes at the expense of the FSB being
stressed out, it will be the bottleneck. I want to propose another
view to this opportunity. Why not put in two cores that use two
different ISA? &lt;/SPAN&gt;&lt;/SPAN&gt;
&lt;/P&gt;

&lt;P align="left"&gt;
&lt;B&gt;Problem&lt;/B&gt;&lt;/P&gt;
&lt;P align="left"&gt;
x86 have lived through a world where we are constantly trying to be
independent from technology, so that we can upgrade to a new
technology when it is present. We don't want to brake our 'legacy'
programs and still we want a new and cleaner ISA.&lt;/P&gt;

&lt;P align="left"&gt;
&lt;B&gt;Solution&lt;/B&gt;&lt;/P&gt;
&lt;P align="left"&gt;
Today we are totally capable of changing an ISA by utilizing the
opportunities we have with multi-cores. Not because we couldn't have
made the same thing with two processors on one motherboard, but this
time it is much cheaper. And not that we don't have solutions for
running different ISA's but this time it is natively done. My
solution is two cores each running it's own ISA without any overhead,
which means running two programs natively in different ISA. 
&lt;/P&gt;
&lt;P align="left"&gt;
With this solution we can still run the 'legacy' code with a 100 %
guarantee that any bug that was present on a pure x86 CPU is still
present on a multi-core CPU with two ISA! 
&lt;/P&gt;

&lt;P align="left"&gt;
&lt;B&gt;Research&lt;/B&gt;&lt;/P&gt;
&lt;P align="left"&gt;
What we need to make this work is a simple operating system that can
detect the different binaries and assigning them to the right core.
They will still run in the same memory, coexists on the same hard
drive. Theoretically this is done easily. The only problem is that we
need a real multi-core CPU that runs two different ISA
simultaneously. Creating a simulation for this simple and elegant
solution would be an overkill because anyone can see that this should
work.&lt;/P&gt;








&lt;P align="left"&gt;
&lt;B&gt;Benefit
for Intel&lt;/B&gt;&lt;/P&gt;
&lt;P align="left"&gt;
Intel can now give a reason to why we need octal core processors.
Also Intel has a once in a lifetime chance to create it's own ISA,
that would make life easier for compilers and the gaming industry
would love some extra registers. Intel would have a nice way of
fazing out x86 code, maybe in 10 years no new code would be written
in x86 but old code could still run as if nothing happened. 
&lt;/P&gt;
&lt;P align="left"&gt;
This is just the tip of the ice berg. Why not make a CPU that has 3-4
different ISA? Stack-based, Register-Register and maybe VLIW? And let
the compiler choose the best ISA for a specific application? 
&lt;/P&gt;

&lt;P align="left"&gt;
&lt;B&gt;Final
thoughts&lt;/B&gt;&lt;/P&gt;
&lt;P align="left"&gt;
I believe this is a really simple solution and can't really
understand why no one hasn't thought about it? Or is there a real
problem behind it that I have missed? Is it something you have
considered and realized that there is not real benefit? I would
really
 be happy if I could hear your response about this.&lt;/P&gt;
&lt;BR /&gt;&lt;BR /&gt;thank you in advance,&lt;BR /&gt;</description>
    <pubDate>Mon, 26 Nov 2007 18:01:04 GMT</pubDate>
    <dc:creator>monthadar</dc:creator>
    <dc:date>2007-11-26T18:01:04Z</dc:date>
    <item>
      <title>fazing out x86, simple solution</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/fazing-out-x86-simple-solution/m-p/887890#M3639</link>
      <description>Hi,&lt;BR /&gt;&lt;BR /&gt;I am a ComputerScience student, and I had an idea that I didn't know where to post. But thankfully to Lexi S. from Intel Software Network Support guided me to post it here.&lt;BR /&gt;&lt;BR /&gt;It seems I can't attach a PDF, so I copied the text. &lt;BR /&gt;&lt;BR /&gt;Me and my friend would be greatefull for any comment/remark on this idea sketch.&lt;BR /&gt;&lt;BR /&gt;------------------------------------------------------------------&lt;BR /&gt;


	
	
	
	

&lt;P align="left"&gt;&lt;U&gt;&lt;B&gt;Abstract:&lt;/B&gt;&lt;/U&gt;&lt;SPAN&gt;&lt;SPAN&gt;
Today everyone asks the question about what are we going to do with
quad or even octal cores? Maybe we can put in a GPU, sound card or
other cool things. But all this comes at the expense of the FSB being
stressed out, it will be the bottleneck. I want to propose another
view to this opportunity. Why not put in two cores that use two
different ISA? &lt;/SPAN&gt;&lt;/SPAN&gt;
&lt;/P&gt;

&lt;P align="left"&gt;
&lt;B&gt;Problem&lt;/B&gt;&lt;/P&gt;
&lt;P align="left"&gt;
x86 have lived through a world where we are constantly trying to be
independent from technology, so that we can upgrade to a new
technology when it is present. We don't want to brake our 'legacy'
programs and still we want a new and cleaner ISA.&lt;/P&gt;

&lt;P align="left"&gt;
&lt;B&gt;Solution&lt;/B&gt;&lt;/P&gt;
&lt;P align="left"&gt;
Today we are totally capable of changing an ISA by utilizing the
opportunities we have with multi-cores. Not because we couldn't have
made the same thing with two processors on one motherboard, but this
time it is much cheaper. And not that we don't have solutions for
running different ISA's but this time it is natively done. My
solution is two cores each running it's own ISA without any overhead,
which means running two programs natively in different ISA. 
&lt;/P&gt;
&lt;P align="left"&gt;
With this solution we can still run the 'legacy' code with a 100 %
guarantee that any bug that was present on a pure x86 CPU is still
present on a multi-core CPU with two ISA! 
&lt;/P&gt;

&lt;P align="left"&gt;
&lt;B&gt;Research&lt;/B&gt;&lt;/P&gt;
&lt;P align="left"&gt;
What we need to make this work is a simple operating system that can
detect the different binaries and assigning them to the right core.
They will still run in the same memory, coexists on the same hard
drive. Theoretically this is done easily. The only problem is that we
need a real multi-core CPU that runs two different ISA
simultaneously. Creating a simulation for this simple and elegant
solution would be an overkill because anyone can see that this should
work.&lt;/P&gt;








&lt;P align="left"&gt;
&lt;B&gt;Benefit
for Intel&lt;/B&gt;&lt;/P&gt;
&lt;P align="left"&gt;
Intel can now give a reason to why we need octal core processors.
Also Intel has a once in a lifetime chance to create it's own ISA,
that would make life easier for compilers and the gaming industry
would love some extra registers. Intel would have a nice way of
fazing out x86 code, maybe in 10 years no new code would be written
in x86 but old code could still run as if nothing happened. 
&lt;/P&gt;
&lt;P align="left"&gt;
This is just the tip of the ice berg. Why not make a CPU that has 3-4
different ISA? Stack-based, Register-Register and maybe VLIW? And let
the compiler choose the best ISA for a specific application? 
&lt;/P&gt;

&lt;P align="left"&gt;
&lt;B&gt;Final
thoughts&lt;/B&gt;&lt;/P&gt;
&lt;P align="left"&gt;
I believe this is a really simple solution and can't really
understand why no one hasn't thought about it? Or is there a real
problem behind it that I have missed? Is it something you have
considered and realized that there is not real benefit? I would
really
 be happy if I could hear your response about this.&lt;/P&gt;
&lt;BR /&gt;&lt;BR /&gt;thank you in advance,&lt;BR /&gt;</description>
      <pubDate>Mon, 26 Nov 2007 18:01:04 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/fazing-out-x86-simple-solution/m-p/887890#M3639</guid>
      <dc:creator>monthadar</dc:creator>
      <dc:date>2007-11-26T18:01:04Z</dc:date>
    </item>
    <item>
      <title>Re: fazing out x86, simple solution</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/fazing-out-x86-simple-solution/m-p/887891#M3640</link>
      <description>if you are interested I have posted this idea at comp.arch:&lt;BR /&gt;&lt;BR /&gt;&lt;A href="http://groups.google.com/group/comp.arch/browse_thread/thread/d397ad7278ff8f3b" target="_blank"&gt;http://groups.google.com/group/comp.arch/browse_thread/thread/d397ad7278ff8f3b&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;and there are some interesting comments.&lt;BR /&gt;&lt;BR /&gt;and thank you for your time.&lt;BR /&gt;</description>
      <pubDate>Thu, 06 Dec 2007 10:29:25 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/fazing-out-x86-simple-solution/m-p/887891#M3640</guid>
      <dc:creator>monthadar</dc:creator>
      <dc:date>2007-12-06T10:29:25Z</dc:date>
    </item>
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