https://community.intel.com/t5/Intel-Moderncode-for-Parallel/MFENCE-and-CLFLUSH/m-p/889064#M3684 <P>I have a question regarding CLFLUSH.</P> <P>Presumably if I code in assembler (or equivilent intrinsics)</P> <P>MFENCE<BR />CLFLUSH [location]<BR />SomeReadInstruction [location]</P> <P>The processor will "drill" through the cache to obtain the contents of [location] (or locations in samecache line as location).</P> <P>The problem I see though is what happens if an interruptand possiblythread context switch occures during the CLFLUSH? i.e. between CFLUSH and SomeReadInstruction.</P> <P>It is potentialy possible that the interrupt, the O/S or read-ahead logic may have populated the cache line and then returning much later resume at SomeReadInstruction and then re-read the now stale cache line.</P> <P>Alternately if I were only interested in read</P> <P>XOR RAX,RAX<BR />MFENCE<BR />LOCK CMPXCHG [location], RAX</P> <P>Is there any sequencing rules such as if MFENCE is followed by CFLUSH, is followed by memory reference instruction that the chain of instructions occure without interruption? If so, then would anyone have these rules? Or the Intel document name?</P> <P>(the rule would have to nip abusive use of the rule such as the CIF problem in the old PDP-8 system)</P> <P>TIA</P> <P>Jim</P> <P></P> <P></P> Tue, 16 Jan 2007 06:44:21 GMT jimdempseyatthecove 2007-01-16T06:44:21Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/MFENCE-and-CLFLUSH/m-p/889064#M3684 <P>I have a question regarding CLFLUSH.</P> <P>Presumably if I code in assembler (or equivilent intrinsics)</P> <P>MFENCE<BR />CLFLUSH [location]<BR />SomeReadInstruction [location]</P> <P>The processor will "drill" through the cache to obtain the contents of [location] (or locations in samecache line as location).</P> <P>The problem I see though is what happens if an interruptand possiblythread context switch occures during the CLFLUSH? i.e. between CFLUSH and SomeReadInstruction.</P> <P>It is potentialy possible that the interrupt, the O/S or read-ahead logic may have populated the cache line and then returning much later resume at SomeReadInstruction and then re-read the now stale cache line.</P> <P>Alternately if I were only interested in read</P> <P>XOR RAX,RAX<BR />MFENCE<BR />LOCK CMPXCHG [location], RAX</P> <P>Is there any sequencing rules such as if MFENCE is followed by CFLUSH, is followed by memory reference instruction that the chain of instructions occure without interruption? If so, then would anyone have these rules? Or the Intel document name?</P> <P>(the rule would have to nip abusive use of the rule such as the CIF problem in the old PDP-8 system)</P> <P>TIA</P> <P>Jim</P> <P></P> <P></P> Tue, 16 Jan 2007 06:44:21 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/MFENCE-and-CLFLUSH/m-p/889064#M3684 jimdempseyatthecove 2007-01-16T06:44:21Z