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    <title>topic multicore performance in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/multicore-performance/m-p/891733#M3804</link>
    <description>any reseach work on bandwidth hungry behaviour of multicore systems ?</description>
    <pubDate>Fri, 29 May 2009 15:52:26 GMT</pubDate>
    <dc:creator>TC2009074</dc:creator>
    <dc:date>2009-05-29T15:52:26Z</dc:date>
    <item>
      <title>multicore performance</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/multicore-performance/m-p/891733#M3804</link>
      <description>any reseach work on bandwidth hungry behaviour of multicore systems ?</description>
      <pubDate>Fri, 29 May 2009 15:52:26 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/multicore-performance/m-p/891733#M3804</guid>
      <dc:creator>TC2009074</dc:creator>
      <dc:date>2009-05-29T15:52:26Z</dc:date>
    </item>
    <item>
      <title>Re: multicore performance</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/multicore-performance/m-p/891734#M3805</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="margin-top: 5px; width: 100%;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/429840"&gt;tc2009074&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;any reseach work on bandwidth hungry behaviour of multicore systems ?&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;Hi tc2009074,&lt;BR /&gt;&lt;BR /&gt;What kind of specific information are you looking for? A comparison against what?&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Mon, 01 Jun 2009 20:00:33 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/multicore-performance/m-p/891734#M3805</guid>
      <dc:creator>gaston-hillar</dc:creator>
      <dc:date>2009-06-01T20:00:33Z</dc:date>
    </item>
    <item>
      <title>Re: multicore performance</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/multicore-performance/m-p/891735#M3806</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="margin-top: 5px; width: 100%;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/176125"&gt;Alain Dominguez (Intel)&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;
&lt;DIV style="margin:0px;"&gt;&lt;/DIV&gt;
&lt;BR /&gt;&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;If you've bandwidth hungry application ==&amp;gt; bandwidth will drive also your scalability.&lt;BR /&gt;&lt;BR /&gt;Generally speaking, you've a maximum global memory bandwidth for your machine (ie: stream benchmark is a good evaluator of it).&lt;BR /&gt;If your application consume xx % of it for 1 thread, you can't expect a scalability greater than 100/xx.&lt;BR /&gt;It's often the case when scalability figures have a "plateau" shape after few threads.&lt;BR /&gt;To avoid this "ceiling" effect, you should:&lt;BR /&gt;- increase your global bandwidth: DIMM,chipset,BIOS settings or machine change (ie)&lt;BR /&gt;- modify your algorithm to diminish pressure on memory ==&amp;gt; even if it's slower at 1 core, you know it could be faster after parallization&lt;BR /&gt;- reorganizing data layout to be more "cachable" and put less pressure on memory&lt;BR /&gt;- etc ... &lt;BR /&gt;&lt;BR /&gt;It's a vast and very interesting subject ==&amp;gt; if you've a description of your application, it could help us to help you&lt;BR /&gt;&lt;BR /&gt;Cheers.</description>
      <pubDate>Thu, 11 Jun 2009 12:29:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/multicore-performance/m-p/891735#M3806</guid>
      <dc:creator>Alain_D_Intel</dc:creator>
      <dc:date>2009-06-11T12:29:06Z</dc:date>
    </item>
    <item>
      <title>Re: multicore performance</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/multicore-performance/m-p/891736#M3807</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="margin-top: 5px; width: 100%;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/176125"&gt;Alain Dominguez (Intel)&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;
&lt;DIV style="margin:0px;"&gt;&lt;/DIV&gt;
&lt;BR /&gt;If you've bandwidth hungry application ==&amp;gt; bandwidth will drive also your scalability.&lt;BR /&gt;&lt;BR /&gt;Generally speaking, you've a maximum global memory bandwidth for your machine (ie: stream benchmark is a good evaluator of it).&lt;BR /&gt;If your application consume xx % of it for 1 thread, you can't expect a scalability greater than 100/xx.&lt;BR /&gt;It's often the case when scalability figures have a "plateau" shape after few threads.&lt;BR /&gt;To avoid this "ceiling" effect, you should:&lt;BR /&gt;- increase your global bandwidth: DIMM,chipset,BIOS settings or machine change (ie)&lt;BR /&gt;- modify your algorithm to diminish pressure on memory ==&amp;gt; even if it's slower at 1 core, you know it could be faster after parallization&lt;BR /&gt;- reorganizing data layout to be more "cachable" and put less pressure on memory&lt;BR /&gt;- etc ... &lt;BR /&gt;&lt;BR /&gt;It's a vast and very interesting subject ==&amp;gt; if you've a description of your application, it could help us to help you&lt;BR /&gt;&lt;BR /&gt;Cheers.&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;Add to the list to experiment with reorganizing the code layout to bemore "cachable" -code for reduced size. Sometimes unrolling of loops will slow down the code due to spill-out of L1 cache.&lt;BR /&gt;&lt;BR /&gt;Jim Dempsey&lt;BR /&gt;</description>
      <pubDate>Thu, 11 Jun 2009 17:16:36 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/multicore-performance/m-p/891736#M3807</guid>
      <dc:creator>jimdempseyatthecove</dc:creator>
      <dc:date>2009-06-11T17:16:36Z</dc:date>
    </item>
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