https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Questions-Regarding-LOCKed-Instructions/m-p/892835#M3855 Got a couple very closely related questions.<BR /> <BR /> The Intel manual says that the P4 relaxed the memory barrier behavior of locked instructions, so that "load operations that reference weakly ordered memory types (such as the WC memory type)" are allowed to cross the barrier (previously, locked instructions were full barriers). This is ambiguous, because WC is THE most weakly ordered memory type, able to do things no other memory type can. So I was wondering if anybody knew how locked instructions behaved with respect to loads from WB memory (the standard application-level memory type) on the P4?<BR /> <BR /> Also, does anyone know how Core 1/2 CPUs behave in this regard? Tue, 19 Dec 2006 02:39:32 GMT catafriggm 2006-12-19T02:39:32Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Questions-Regarding-LOCKed-Instructions/m-p/892835#M3855 Got a couple very closely related questions.<BR /> <BR /> The Intel manual says that the P4 relaxed the memory barrier behavior of locked instructions, so that "load operations that reference weakly ordered memory types (such as the WC memory type)" are allowed to cross the barrier (previously, locked instructions were full barriers). This is ambiguous, because WC is THE most weakly ordered memory type, able to do things no other memory type can. So I was wondering if anybody knew how locked instructions behaved with respect to loads from WB memory (the standard application-level memory type) on the P4?<BR /> <BR /> Also, does anyone know how Core 1/2 CPUs behave in this regard? Tue, 19 Dec 2006 02:39:32 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Questions-Regarding-LOCKed-Instructions/m-p/892835#M3855 catafriggm 2006-12-19T02:39:32Z