<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic invalidate cache in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/invalidate-cache/m-p/897050#M4064</link>
    <description>Hi&lt;BR /&gt;&lt;BR /&gt;I have to write a program in C for test the  different execution time with use of the cache warm or cold.&lt;BR /&gt;&lt;BR /&gt;I have use the directive &lt;I&gt;asm("clflush (%0)"::"r"(m)); &lt;/I&gt;for invalidate all the line that contains the address of the vector that i want read (m), but the time of read is substantially the same whitout the flush !&lt;BR /&gt;&lt;BR /&gt;where i wrong ? &lt;BR /&gt;i test a dual core duo whit 32 Kb - L1 chace 64 byte line size.&lt;BR /&gt;&lt;BR /&gt;report the code for explain :&lt;I&gt;&lt;BR /&gt;&lt;BR /&gt;for ( i=0; i&lt;SIZE&gt; { asm("clflush (%0)"::"r"(v+i)); }&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;gettimeofday(&amp;amp;start,NULL);&lt;BR /&gt;for ( i=0; i&lt;SIZE&gt;{ &lt;BR /&gt; sum += compute(v&lt;I&gt;));&lt;BR /&gt;}&lt;BR /&gt;gettimeofday(&amp;amp;stop,NULL);&lt;BR /&gt;&lt;BR /&gt;&lt;/I&gt;thank you !!!!&lt;I&gt;&lt;BR /&gt;&lt;/I&gt;&lt;/SIZE&gt;&lt;/SIZE&gt;&lt;/I&gt;</description>
    <pubDate>Sat, 26 Apr 2008 11:35:04 GMT</pubDate>
    <dc:creator>morisaki</dc:creator>
    <dc:date>2008-04-26T11:35:04Z</dc:date>
    <item>
      <title>invalidate cache</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/invalidate-cache/m-p/897050#M4064</link>
      <description>Hi&lt;BR /&gt;&lt;BR /&gt;I have to write a program in C for test the  different execution time with use of the cache warm or cold.&lt;BR /&gt;&lt;BR /&gt;I have use the directive &lt;I&gt;asm("clflush (%0)"::"r"(m)); &lt;/I&gt;for invalidate all the line that contains the address of the vector that i want read (m), but the time of read is substantially the same whitout the flush !&lt;BR /&gt;&lt;BR /&gt;where i wrong ? &lt;BR /&gt;i test a dual core duo whit 32 Kb - L1 chace 64 byte line size.&lt;BR /&gt;&lt;BR /&gt;report the code for explain :&lt;I&gt;&lt;BR /&gt;&lt;BR /&gt;for ( i=0; i&lt;SIZE&gt; { asm("clflush (%0)"::"r"(v+i)); }&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;gettimeofday(&amp;amp;start,NULL);&lt;BR /&gt;for ( i=0; i&lt;SIZE&gt;{ &lt;BR /&gt; sum += compute(v&lt;I&gt;));&lt;BR /&gt;}&lt;BR /&gt;gettimeofday(&amp;amp;stop,NULL);&lt;BR /&gt;&lt;BR /&gt;&lt;/I&gt;thank you !!!!&lt;I&gt;&lt;BR /&gt;&lt;/I&gt;&lt;/SIZE&gt;&lt;/SIZE&gt;&lt;/I&gt;</description>
      <pubDate>Sat, 26 Apr 2008 11:35:04 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/invalidate-cache/m-p/897050#M4064</guid>
      <dc:creator>morisaki</dc:creator>
      <dc:date>2008-04-26T11:35:04Z</dc:date>
    </item>
    <item>
      <title>Re: invalidate cache</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/invalidate-cache/m-p/897051#M4065</link>
      <description>If you have the normal setting of hardware prefetch, flushing cache could affect only the time required to get the first 2 cache lines or so of each page. I suppose that cache miss timing tests would be done with more irregular access patterns. You could look at how it was done with lmbench.&lt;BR /&gt;</description>
      <pubDate>Sat, 26 Apr 2008 22:44:54 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/invalidate-cache/m-p/897051#M4065</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2008-04-26T22:44:54Z</dc:date>
    </item>
  </channel>
</rss>

