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    <title>topic Re: Multi-producer/multi-consumer SEH-based queue in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897715#M4076</link>
    <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/347331"&gt;Dmitriy Vyukov&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt; &lt;BR /&gt;Here is the test I used for verification:&lt;BR /&gt;&lt;A href="http://relacy.pastebin.com/f5df9dcfa"&gt;http://relacy.pastebin.com/f5df9dcfa&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;The test does not detect any problems.&lt;BR /&gt;Unfortunately it uses new not yet published syntax, but at least you may use it as a base.&lt;BR /&gt;I express the load as:&lt;BR /&gt;&lt;BR /&gt;
&lt;/EM&gt;&lt;PRE&gt;&lt;EM&gt;[cpp]        head_t h1 = head_.next_.load(std::memory_order_acquire);
        head_t h2 = head_.next_.load(std::memory_order_acquire);
        head_t h (0, 0);
        if (rl::rand(2) == 0)
        {
            h.ptr_= h1.ptr_;
            h.cnt_ = h2.cnt_;
        }
        else
        {
            h.ptr_= h2.ptr_;
            h.cnt_ = h1.cnt_;
        }
[/cpp]&lt;/EM&gt;&lt;/PRE&gt;
&lt;BR /&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;I will try and convert the example code to Relacy 1.5.0. BTW, how did you eliminate the need for `$'&lt;SPAN style="font-family: Verdana;"&gt;? That's really cool! Anyway, I have one comment. I notice that you are performing the "out-of-order" load only one time, then you enter the "DWCAS loop" and never perform it again upon DWCAS failure. That will not give much of a window for the race, if any, to occur. Might I suggest that you rework the algorithm such that the "out-of-order" load occurs on every iteration of the loop. Something like:&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;BR /&gt;&lt;BR /&gt;
&lt;PRE&gt;[cpp]    node_t* dequeue()
    {
        for (;;)
        {
            head_t h1 = head_.next_.load(std::memory_order_acquire);
            head_t h2 = head_.next_.load(std::memory_order_acquire);
            head_t h (0, 0);
            if (rl::rand(2) == 0)
            {
                h.ptr_= h1.ptr_;
                h.cnt_ = h2.cnt_;
            }
            else
            {
                h.ptr_= h2.ptr_;
                h.cnt_ = h1.cnt_;
            }
            // [...]
        }
        // [...]
    }[/cpp]&lt;/PRE&gt;
&lt;BR /&gt;
&lt;DIV&gt;Or perhaps even:&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;
&lt;PRE&gt;[cpp]&lt;PRE name="code" class="cpp"&gt;    node_t* dequeue()
    {
        rl::backoff b;
        for (;;)
        {
            head_t h (0, 0);
            head_t h1 = head_.next_.load(std::memory_order_acquire);
            h.ptr = h1.ptr_
            b.yield();
            head_t h2 = head_.next_.load(std::memory_order_acquire);
            h.cnt = h2.cnt_
            // [...]
        }
        // [...]
    }[/cpp]&lt;/PRE&gt;
&lt;/PRE&gt;
&lt;/DIV&gt;</description>
    <pubDate>Fri, 21 Aug 2009 13:17:51 GMT</pubDate>
    <dc:creator>Chris_M__Thomasson</dc:creator>
    <dc:date>2009-08-21T13:17:51Z</dc:date>
    <item>
      <title>Multi-producer/multi-consumer SEH-based queue</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897711#M4072</link>
      <description>I've posted novel multi-producer/multi-consumer queue algorithm here:&lt;BR /&gt;&lt;A href="http://software.intel.com/en-us/blogs/2009/08/11/multi-producermulti-consumer-seh-based-queue/"&gt;http://software.intel.com/en-us/blogs/2009/08/11/multi-producermulti-consumer-seh-based-queue/&lt;/A&gt;&lt;BR /&gt;The algorithm has quite appealing characteristics:&lt;BR /&gt; - intrusive&lt;BR /&gt; - producers: 1 XCHG, wait-free&lt;BR /&gt; - consumers: 1 CAS on common path, mostly lock-free&lt;BR /&gt; - producers and consumers do not contend with each other (until queue is empty)&lt;BR /&gt; - no need for safe memory reclamation&lt;BR /&gt;I bet it will beat Michael and Scott queue to death in every way.&lt;BR /&gt;If you are interested we may discuss it here.&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Wed, 12 Aug 2009 06:32:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897711#M4072</guid>
      <dc:creator>Dmitry_Vyukov</dc:creator>
      <dc:date>2009-08-12T06:32:52Z</dc:date>
    </item>
    <item>
      <title>Re: Multi-producer/multi-consumer SEH-based queue</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897712#M4073</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/347331"&gt;Dmitriy Vyukov&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;I've posted novel multi-producer/multi-consumer queue algorithm here:&lt;BR /&gt;&lt;A href="http://software.intel.com/en-us/blogs/2009/08/11/multi-producermulti-consumer-seh-based-queue/"&gt;http://software.intel.com/en-us/blogs/2009/08/11/multi-producermulti-consumer-seh-based-queue/&lt;/A&gt;&lt;BR /&gt;The algorithm has quite appealing characteristics:&lt;BR /&gt; - intrusive&lt;BR /&gt; - producers: 1 XCHG, wait-free&lt;BR /&gt; - consumers: 1 CAS on common path, mostly lock-free&lt;BR /&gt; - producers and consumers do not contend with each other (until queue is empty)&lt;BR /&gt; - no need for safe memory reclamation&lt;BR /&gt;I bet it will beat Michael and Scott queue to death in every way.&lt;BR /&gt;If you are interested we may discuss it here.&lt;BR /&gt;&lt;BR /&gt;&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;
&lt;DIV&gt;FWIW, here is a link to a previous disscussion in `comp.programming.threads':&lt;BR /&gt;&lt;BR /&gt;&lt;A href="http://groups.google.com/group/comp.programming.threads/browse_frm/thread/c43d1197c8168b4e"&gt;http://groups.google.com/group/comp.programming.threads/browse_frm/thread/c43d1197c8168b4e&lt;/A&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;The intrusive nature of the queue is extremely attractive indeed. Also, the wait-free nature of push is basically unbeatable. No PDR == very NICE! With regard to comparing it to Michael and Scott queue, well, it's going to devastate it an all fronts. I am sure of that, no testing is even needed!&lt;BR /&gt;&lt;BR /&gt;;^)&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;Also, FWIW, here is the version that I created which does require memory management and is not intrusive:&lt;BR /&gt;&lt;BR /&gt;&lt;A href="http://software.intel.com/en-us/forums/showthread.php?t=66573"&gt;http://software.intel.com/en-us/forums/showthread.php?t=66573&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;And here is a full-blown example implmentation in C#:&lt;BR /&gt;&lt;BR /&gt;&lt;A href="http://cpt.pastebin.com/f72cc3cc1"&gt;http://cpt.pastebin.com/f72cc3cc1&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;A href="http://cpt.pastebin.com/f72cc3cc1"&gt;&lt;/A&gt;And of course, the implmentation in Relacy Race Detector:&lt;BR /&gt;&lt;BR /&gt;&lt;A href="http://relacy.pastebin.com/f59d6ff2b"&gt;http://relacy.pastebin.com/f59d6ff2b&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;The non-intrusive nature of my version is simpler, however that does not mean it's better...&lt;/DIV&gt;</description>
      <pubDate>Wed, 12 Aug 2009 16:13:28 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897712#M4073</guid>
      <dc:creator>Chris_M__Thomasson</dc:creator>
      <dc:date>2009-08-12T16:13:28Z</dc:date>
    </item>
    <item>
      <title>Re: Multi-producer/multi-consumer SEH-based queue</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897713#M4074</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/347331"&gt;Dmitriy Vyukov&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;I've posted novel multi-producer/multi-consumer queue algorithm here:&lt;BR /&gt;&lt;A href="http://software.intel.com/en-us/blogs/2009/08/11/multi-producermulti-consumer-seh-based-queue/"&gt;http://software.intel.com/en-us/blogs/2009/08/11/multi-producermulti-consumer-seh-based-queue/&lt;/A&gt;&lt;BR /&gt;The algorithm has quite appealing characteristics:&lt;BR /&gt; - intrusive&lt;BR /&gt; - producers: 1 XCHG, wait-free&lt;BR /&gt; - consumers: 1 CAS on common path, mostly lock-free&lt;BR /&gt; - producers and consumers do not contend with each other (until queue is empty)&lt;BR /&gt; - no need for safe memory reclamation&lt;BR /&gt;I bet it will beat Michael and Scott queue to death in every way.&lt;BR /&gt;If you are interested we may discuss it here.&lt;BR /&gt;&lt;BR /&gt;&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;Please note that there is a race-condition in the non-intrusive version of the algorithm I posted IF, and ONLY IF, you read the tail pointer BEFORE the tail aba counter. Here is explanation and Relacy source-code which proves it:&lt;BR /&gt;&lt;BR /&gt;&lt;A href="http://groups.google.com/group/comp.programming.threads/msg/62527c65a440516a" target="_blank"&gt;http://groups.google.com/group/comp.programming.threads/msg/62527c65a440516a&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;A href="http://relacy.pastebin.com/f4b57bda2" target="_blank"&gt;http://relacy.pastebin.com/f4b57bda2&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;I am pretty sure that this will effect Dmitriy's algorithm as well as he is loading pointer BEFORE aba counter. However, I need to model his algorithm in Relacy before I give definitive answer.&lt;BR /&gt;&lt;/DIV&gt;</description>
      <pubDate>Thu, 13 Aug 2009 01:25:26 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897713#M4074</guid>
      <dc:creator>Chris_M__Thomasson</dc:creator>
      <dc:date>2009-08-13T01:25:26Z</dc:date>
    </item>
    <item>
      <title>Re: Multi-producer/multi-consumer SEH-based queue</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897714#M4075</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/6002"&gt;Chris M. Thomasson&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt;
&lt;DIV&gt;&lt;BR /&gt;I am pretty sure that this will effect Dmitriy's algorithm as well as he is loading pointer BEFORE aba counter. However, I need to model his algorithm in Relacy before I give definitive answer.&lt;BR /&gt;&lt;/DIV&gt;
&lt;/EM&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;Here is the test I used for verification:&lt;BR /&gt;&lt;A href="http://relacy.pastebin.com/f5df9dcfa"&gt;http://relacy.pastebin.com/f5df9dcfa&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;The test does not detect any problems.&lt;BR /&gt;Unfortunately it uses new not yet published syntax, but at least you may use it as a base.&lt;BR /&gt;I express the load as:&lt;BR /&gt;&lt;BR /&gt;
&lt;PRE&gt;[cpp]        head_t h1 = head_.next_.load(std::memory_order_acquire);
        head_t h2 = head_.next_.load(std::memory_order_acquire);
        head_t h (0, 0);
        if (rl::rand(2) == 0)
        {
            h.ptr_= h1.ptr_;
            h.cnt_ = h2.cnt_;
        }
        else
        {
            h.ptr_= h2.ptr_;
            h.cnt_ = h1.cnt_;
        }
[/cpp]&lt;/PRE&gt;
&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Thu, 13 Aug 2009 23:20:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897714#M4075</guid>
      <dc:creator>Dmitry_Vyukov</dc:creator>
      <dc:date>2009-08-13T23:20:45Z</dc:date>
    </item>
    <item>
      <title>Re: Multi-producer/multi-consumer SEH-based queue</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897715#M4076</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/347331"&gt;Dmitriy Vyukov&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;EM&gt; &lt;BR /&gt;Here is the test I used for verification:&lt;BR /&gt;&lt;A href="http://relacy.pastebin.com/f5df9dcfa"&gt;http://relacy.pastebin.com/f5df9dcfa&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;The test does not detect any problems.&lt;BR /&gt;Unfortunately it uses new not yet published syntax, but at least you may use it as a base.&lt;BR /&gt;I express the load as:&lt;BR /&gt;&lt;BR /&gt;
&lt;/EM&gt;&lt;PRE&gt;&lt;EM&gt;[cpp]        head_t h1 = head_.next_.load(std::memory_order_acquire);
        head_t h2 = head_.next_.load(std::memory_order_acquire);
        head_t h (0, 0);
        if (rl::rand(2) == 0)
        {
            h.ptr_= h1.ptr_;
            h.cnt_ = h2.cnt_;
        }
        else
        {
            h.ptr_= h2.ptr_;
            h.cnt_ = h1.cnt_;
        }
[/cpp]&lt;/EM&gt;&lt;/PRE&gt;
&lt;BR /&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;
&lt;DIV&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;I will try and convert the example code to Relacy 1.5.0. BTW, how did you eliminate the need for `$'&lt;SPAN style="font-family: Verdana;"&gt;? That's really cool! Anyway, I have one comment. I notice that you are performing the "out-of-order" load only one time, then you enter the "DWCAS loop" and never perform it again upon DWCAS failure. That will not give much of a window for the race, if any, to occur. Might I suggest that you rework the algorithm such that the "out-of-order" load occurs on every iteration of the loop. Something like:&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;BR /&gt;&lt;BR /&gt;
&lt;PRE&gt;[cpp]    node_t* dequeue()
    {
        for (;;)
        {
            head_t h1 = head_.next_.load(std::memory_order_acquire);
            head_t h2 = head_.next_.load(std::memory_order_acquire);
            head_t h (0, 0);
            if (rl::rand(2) == 0)
            {
                h.ptr_= h1.ptr_;
                h.cnt_ = h2.cnt_;
            }
            else
            {
                h.ptr_= h2.ptr_;
                h.cnt_ = h1.cnt_;
            }
            // [...]
        }
        // [...]
    }[/cpp]&lt;/PRE&gt;
&lt;BR /&gt;
&lt;DIV&gt;Or perhaps even:&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;
&lt;PRE&gt;[cpp]&lt;PRE name="code" class="cpp"&gt;    node_t* dequeue()
    {
        rl::backoff b;
        for (;;)
        {
            head_t h (0, 0);
            head_t h1 = head_.next_.load(std::memory_order_acquire);
            h.ptr = h1.ptr_
            b.yield();
            head_t h2 = head_.next_.load(std::memory_order_acquire);
            h.cnt = h2.cnt_
            // [...]
        }
        // [...]
    }[/cpp]&lt;/PRE&gt;
&lt;/PRE&gt;
&lt;/DIV&gt;</description>
      <pubDate>Fri, 21 Aug 2009 13:17:51 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897715#M4076</guid>
      <dc:creator>Chris_M__Thomasson</dc:creator>
      <dc:date>2009-08-21T13:17:51Z</dc:date>
    </item>
    <item>
      <title>Re: Multi-producer/multi-consumer SEH-based queue</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897716#M4077</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/6002"&gt;Chris M. Thomasson&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;I will try and convert the example code to Relacy 1.5.0. BTW, how did you eliminate the need for `$'&lt;SPAN style="font-family: Verdana;"&gt;? That's really cool! &lt;/SPAN&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;#define memory_order_XXX mo_XXX, $&lt;BR /&gt;&lt;BR /&gt;The same for all WinAPI/POSIX functions, i.e.:&lt;BR /&gt;&lt;BR /&gt;#define WaitForSingleObject(obj, timeout) rl::rl_WaitForSingleObject(obj, timeout, $)&lt;BR /&gt;&lt;BR /&gt;There are still some place where one has to use macros:&lt;BR /&gt;1. Declaration/accesses to plain vars:&lt;BR /&gt;DECL_VAR(int) x;&lt;BR /&gt;VAR(x) = 1;&lt;BR /&gt;2. Declaration/accesses to thread local vars:&lt;BR /&gt;DECL_TLS(int) y;&lt;BR /&gt;TLS(y) = 1;&lt;BR /&gt;3. Memory management functions:&lt;BR /&gt;NEW(int) (0);&lt;BR /&gt;DEL(p);&lt;BR /&gt;(hmm... I think I may redefine new/delete too)&lt;BR /&gt;&lt;BR /&gt;Btw, I am going to publish next version under BSD style licence w/o any additional clauses.&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Fri, 04 Sep 2009 19:50:27 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897716#M4077</guid>
      <dc:creator>Dmitry_Vyukov</dc:creator>
      <dc:date>2009-09-04T19:50:27Z</dc:date>
    </item>
    <item>
      <title>Re: Multi-producer/multi-consumer SEH-based queue</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897717#M4078</link>
      <description>&lt;DIV style="margin:0px;"&gt;
&lt;DIV id="quote_reply" style="width: 100%; margin-top: 5px;"&gt;
&lt;DIV style="margin-left:2px;margin-right:2px;"&gt;Quoting - &lt;A href="https://community.intel.com/en-us/profile/6002"&gt;Chris M. Thomasson&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV style="background-color:#E5E5E5; padding:5px;border: 1px; border-style: inset;margin-left:2px;margin-right:2px;"&gt;&lt;SPAN style="font-family: Verdana;"&gt;Anyway, I have one comment. I notice that you are performing the "out-of-order" load only one time, then you enter the "DWCAS loop" and never perform it again upon DWCAS failure. That will not give much of a window for the race, if any, to occur. Might I suggest that you rework the algorithm such that the "out-of-order" load occurs on every iteration of the loop.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;/DIV&gt;
&lt;BR /&gt;Yes, of course, this will be better. I was just lazy :)&lt;BR /&gt;&lt;BR /&gt;</description>
      <pubDate>Fri, 04 Sep 2009 19:51:55 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Multi-producer-multi-consumer-SEH-based-queue/m-p/897717#M4078</guid>
      <dc:creator>Dmitry_Vyukov</dc:creator>
      <dc:date>2009-09-04T19:51:55Z</dc:date>
    </item>
  </channel>
</rss>

