https://community.intel.com/t5/Intel-Moderncode-for-Parallel/MicroArchitectural-Information-on-IntelCore2Duo-E6400/m-p/901216#M4249 Many of these items are the same as other Core architecture variants, such as Woodcrest. I know of only the one set of docs covering all of them. <BR />For TLB miss latency, there are several cases, which I doubt have been documented fully on any of these CPUs. Note the 2 levels of TLB and the 2 different designations of cache levels (0/1 and 1/2).<BR />In case you didn't see it, you might find this interesting:<BR /><A href="https://community.intel.com/file/944">http://software.intel.com/file/944</A><BR />I note that it doesn't necessarily agree with other docs; for example, it says the small DTLB has 8 entries, where I've seen 16 written elsewhere. Nor can I explain why it talks about L0, L1, and L2.<BR /> Mon, 21 Apr 2008 12:59:15 GMT TimP 2008-04-21T12:59:15Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/MicroArchitectural-Information-on-IntelCore2Duo-E6400/m-p/901215#M4248 Hello,<BR />I wanted some information regarding the microarchitecural specifications of Intel Core 2 Duo E6000 series (specifically E6400) Desktop Computer. I looked for them in a lot of Intel's docs but couldnot find them. Here are the questions. What is its?<BR />1. Issue width<BR />2.Decode width<BR />3.Load/Store queue<BR />4.Memory Access Latency <BR />5.Memory Access Bus width<BR />6.Instruction TLB<BR />7.Data TLB<BR />8.Total No. of Integer/Multiplier/Divider<BR />9.Memory System ports<BR />10.No. of Floating Point ALU<BR />11.F.P. Mul/Div<BR />12.Instrn/Data TLB miss latency<BR />Thanks,<BR />prads<BR /> Mon, 21 Apr 2008 11:08:08 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/MicroArchitectural-Information-on-IntelCore2Duo-E6400/m-p/901215#M4248 prads 2008-04-21T11:08:08Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/MicroArchitectural-Information-on-IntelCore2Duo-E6400/m-p/901216#M4249 Many of these items are the same as other Core architecture variants, such as Woodcrest. I know of only the one set of docs covering all of them. <BR />For TLB miss latency, there are several cases, which I doubt have been documented fully on any of these CPUs. Note the 2 levels of TLB and the 2 different designations of cache levels (0/1 and 1/2).<BR />In case you didn't see it, you might find this interesting:<BR /><A href="https://community.intel.com/file/944">http://software.intel.com/file/944</A><BR />I note that it doesn't necessarily agree with other docs; for example, it says the small DTLB has 8 entries, where I've seen 16 written elsewhere. Nor can I explain why it talks about L0, L1, and L2.<BR /> Mon, 21 Apr 2008 12:59:15 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/MicroArchitectural-Information-on-IntelCore2Duo-E6400/m-p/901216#M4249 TimP 2008-04-21T12:59:15Z