<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: When cache locking occur? in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/When-cache-locking-occur/m-p/907659#M4492</link>
    <description>Are here any specialists on Intel multicore processors?&lt;BR /&gt;Maybe Intel has *another* forum, where Intel's specialists answering to  community questions about Intel processors? ...&lt;BR /&gt;&lt;BR /&gt;Dmitriy V'jukov&lt;BR /&gt;</description>
    <pubDate>Thu, 04 Oct 2007 19:56:19 GMT</pubDate>
    <dc:creator>Dmitry_Vyukov</dc:creator>
    <dc:date>2007-10-04T19:56:19Z</dc:date>
    <item>
      <title>When cache locking occur?</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/When-cache-locking-occur/m-p/907658#M4491</link>
      <description>When cache locking exactly occur?&lt;BR /&gt;When data reside in *current* core's cache? Or when data reside in *any* core's cache? Or when cache line have some particular status? Or when?&lt;BR /&gt;&lt;BR /&gt;Dmitriy V'jukov&lt;BR /&gt;</description>
      <pubDate>Sat, 22 Sep 2007 19:50:42 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/When-cache-locking-occur/m-p/907658#M4491</guid>
      <dc:creator>Dmitry_Vyukov</dc:creator>
      <dc:date>2007-09-22T19:50:42Z</dc:date>
    </item>
    <item>
      <title>Re: When cache locking occur?</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/When-cache-locking-occur/m-p/907659#M4492</link>
      <description>Are here any specialists on Intel multicore processors?&lt;BR /&gt;Maybe Intel has *another* forum, where Intel's specialists answering to  community questions about Intel processors? ...&lt;BR /&gt;&lt;BR /&gt;Dmitriy V'jukov&lt;BR /&gt;</description>
      <pubDate>Thu, 04 Oct 2007 19:56:19 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/When-cache-locking-occur/m-p/907659#M4492</guid>
      <dc:creator>Dmitry_Vyukov</dc:creator>
      <dc:date>2007-10-04T19:56:19Z</dc:date>
    </item>
    <item>
      <title>Re: When cache locking occur?</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/When-cache-locking-occur/m-p/907660#M4493</link>
      <description>&lt;P&gt;what do you mean by "when"? the cache line that the program tries to lock can be initially at any place including memory or the disk,and will be brought to the current core's cache once accessed by the locking instruction.&lt;/P&gt;</description>
      <pubDate>Mon, 05 Nov 2007 20:25:06 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/When-cache-locking-occur/m-p/907660#M4493</guid>
      <dc:creator>Anat_S_Intel</dc:creator>
      <dc:date>2007-11-05T20:25:06Z</dc:date>
    </item>
    <item>
      <title>Re: When cache locking occur?</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/When-cache-locking-occur/m-p/907661#M4494</link>
      <description>&lt;BLOCKQUOTE&gt;&lt;DIV&gt;&lt;IMG src="https://community.intel.com/file/6745" /&gt; &lt;STRONG&gt;anshgm:&lt;/STRONG&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;P&gt;what do you mean by "when"? the cache line that the program tries to lock can be initially at any place including memory or the disk,and will be brought to the current core's cache once accessed by the locking instruction.&lt;/P&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;BR /&gt;&lt;BR /&gt;Let's assume cache line in current core cache, or in foreign core cache, or in both. I.e. memory location actively used by program. Are there any techniques to increase probability of cache line locking instead of bus locking? I mean techniques from point of view of system programmer.&lt;BR /&gt;&lt;BR /&gt;For example, if cache line in current core cache in modified or exclusive state then cache line locking WILL occur.&lt;BR /&gt;Or if cache line in ANY core cache  in modified or exclusive state then cache line locking WILL occur.&lt;BR /&gt;Or if cache line in shared state then cache line locking WILL occur.&lt;BR /&gt;
&lt;BR /&gt;Dmitriy V'jukov&lt;BR /&gt;</description>
      <pubDate>Tue, 06 Nov 2007 08:12:05 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/When-cache-locking-occur/m-p/907661#M4494</guid>
      <dc:creator>Dmitry_Vyukov</dc:creator>
      <dc:date>2007-11-06T08:12:05Z</dc:date>
    </item>
  </channel>
</rss>

