topic Thread Data Exchange through L3 Cache in Intel® Moderncode for Parallel Architectures

Thread Data Exchange through L3 Cache

bmeardon — Tue, 22 Feb 2011 23:06:18 GMT

Hello,

I have hopefully a quick question...

I'm using a dual socket quad core (HT) Xeon X5570. It is a NUMA machine with each core having its own L1 and L2 caches and each socket's cores share a single L3 cache on the die. My question revolves around access and coherence specifically with the shared L3 cache.

I'm looking to have the most efficient communication between threads that will only run on cores on the same socket sharing the same L3 cache. I'm looking to do this through having a shared memory block (an array) that is only accessed by threads on the same socket/L3 cache. If only these threads access this array (so no other cores on different sockets will access it), will write backs to main memory be required? I'm intersted in what the specific cache coherency mechanics will be under this scenario?

Thanks for your help.

Regards,

Brandon

Thread Data Exchange through L3 Cache

TimP — Wed, 23 Feb 2011 18:31:24 GMT

I guess you are asking about the situation where a thread modifies a cache line, then other threads on other cores want to read it. The updated cache line in L1 or L2 becomes the only copy which is valid, and it must be updated by copying to L3 before other cores can use it by updating their copy in L1 or L2. Cores on the same CPU don't need to wait for write back to memory, as cores on the other CPU must do.

Thread Data Exchange through L3 Cache

bmeardon — Wed, 23 Feb 2011 18:54:52 GMT

I thought that would be the answer and that confirms it. Thank you TimP!