topic Re: Avoiding cache collisions between threads in Intel® Moderncode for Parallel Architectures

Avoiding cache collisions between threads

anonymouscoward — Wed, 15 Dec 2004 14:20:44 GMT

On Intel processors with hyperthreading support, is there any way to avoid having one thread evict cache lines belonging to the other thread? Ideally, I'd like to split the L1 data cache (and maybe other caches as well) in half, changing it from an 8kB 4-way associative cache to two 4kB 2-way associative cache.

The only reference I've been able to find to controlling caching interaction with hyperthreading is bit 24 of IA32_MISC_ENABLE, which controls whether threads can access entries "owned" by the other thread; this does not satisfy my requirements.

Re: Avoiding cache collisions between threads

ClayB — Tue, 21 Dec 2004 05:04:20 GMT

AnonymousC -

Unfortunately, there is no way to do this on a Hyper-Threading enabled system. The caches are shared resources on HT processors. Other parts of the processor architecture are split between the logical processors when HT is enabled; all three levels of the cache resources are not.

For more info on HT and the disposition of resources within an HT processor, see the Intel Technology Journal at http://www.intel.com/technology/itj/2002/volume06issue01/art01_hyper/p01_abstract.htm.

-- clay

Re: Avoiding cache collisions between threads

anonymouscoward — Tue, 21 Dec 2004 13:54:58 GMT

ClayB wrote:

AnonymousC -

Unfortunately, there is no way to do this on a Hyper-Threading enabled system.

*sigh*

I was hoping that there might be some way around this; I guess I'll just have to disable hyperthreading instead.

If anyone knows of any undocumented solution (e.g., using a "reserved" MSR), please let me know...

/me wouldn't mind hearing if this behaviour could be changed using a microcode patch, either.