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    <title>topic Searched and honored. I will in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/NUMA-and-Linux-Page-Cache/m-p/935523#M5020</link>
    <description>&lt;P&gt;Searched and honored.&amp;nbsp;I will try to answer to its own question. As I understand it, this Linux mechanism is called replication page cache (replication page cache between NUMA nodes). Unfortunately there is no time to try it. So the question remains whether it is effective and whether there any other problems?&lt;/P&gt;
&lt;P&gt;Thanks to all who are interested&lt;/P&gt;</description>
    <pubDate>Thu, 04 Jul 2013 14:50:32 GMT</pubDate>
    <dc:creator>SB17</dc:creator>
    <dc:date>2013-07-04T14:50:32Z</dc:date>
    <item>
      <title>NUMA and Linux Page Cache</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/NUMA-and-Linux-Page-Cache/m-p/935520#M5017</link>
      <description>&lt;P&gt;sorry for the stupid question, but&lt;/P&gt;
&lt;P&gt;if I have a linux system and the Numa, I perform a write operation to the disk, the file is cached in in Linux (page cache).&amp;nbsp;Knows another Numa node (socket) that the file is already in the cache or it will read it from the disk? If another node knows that the file is in the cache - does this mean that every Numa node will constantly poll the central table&amp;nbsp;some cached data or it is running as it differently?&lt;/P&gt;
&lt;P&gt;Thank you for your attention to my problem&lt;/P&gt;</description>
      <pubDate>Thu, 27 Jun 2013 13:55:37 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/NUMA-and-Linux-Page-Cache/m-p/935520#M5017</guid>
      <dc:creator>SB17</dc:creator>
      <dc:date>2013-06-27T13:55:37Z</dc:date>
    </item>
    <item>
      <title>Do you mean NUMA CC - cache</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/NUMA-and-Linux-Page-Cache/m-p/935521#M5018</link>
      <description>&lt;P&gt;Do you mean NUMA CC - cache coherency?&lt;/P&gt;</description>
      <pubDate>Fri, 28 Jun 2013 06:01:49 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/NUMA-and-Linux-Page-Cache/m-p/935521#M5018</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-06-28T06:01:49Z</dc:date>
    </item>
    <item>
      <title>yes</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/NUMA-and-Linux-Page-Cache/m-p/935522#M5019</link>
      <description>&lt;P&gt;yes&lt;/P&gt;</description>
      <pubDate>Fri, 28 Jun 2013 14:03:32 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/NUMA-and-Linux-Page-Cache/m-p/935522#M5019</guid>
      <dc:creator>SB17</dc:creator>
      <dc:date>2013-06-28T14:03:32Z</dc:date>
    </item>
    <item>
      <title>Searched and honored. I will</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/NUMA-and-Linux-Page-Cache/m-p/935523#M5020</link>
      <description>&lt;P&gt;Searched and honored.&amp;nbsp;I will try to answer to its own question. As I understand it, this Linux mechanism is called replication page cache (replication page cache between NUMA nodes). Unfortunately there is no time to try it. So the question remains whether it is effective and whether there any other problems?&lt;/P&gt;
&lt;P&gt;Thanks to all who are interested&lt;/P&gt;</description>
      <pubDate>Thu, 04 Jul 2013 14:50:32 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/NUMA-and-Linux-Page-Cache/m-p/935523#M5020</guid>
      <dc:creator>SB17</dc:creator>
      <dc:date>2013-07-04T14:50:32Z</dc:date>
    </item>
    <item>
      <title>I am confused on this too.</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/NUMA-and-Linux-Page-Cache/m-p/935524#M5021</link>
      <description>&lt;P&gt;I am confused on this too. Any help will be appreciated.&lt;/P&gt;</description>
      <pubDate>Sat, 06 Jul 2013 16:29:16 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/NUMA-and-Linux-Page-Cache/m-p/935524#M5021</guid>
      <dc:creator>Kim_J_</dc:creator>
      <dc:date>2013-07-06T16:29:16Z</dc:date>
    </item>
    <item>
      <title>What kind is the purpose of</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/NUMA-and-Linux-Page-Cache/m-p/935525#M5022</link>
      <description>&lt;P&gt;What kind is the purpose of your research? What a work load profile intends to accelerate (such as a file server, database, virtualization)? Unfortunately I'm still stuck on the study of features of Linux on the Numa-aware implementation and has not yet started to learn page cache. I think the work load profile should be as less intense and focused on reading, but not change, then we can expect any positive results.&lt;/P&gt;</description>
      <pubDate>Sun, 07 Jul 2013 16:51:09 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/NUMA-and-Linux-Page-Cache/m-p/935525#M5022</guid>
      <dc:creator>SB17</dc:creator>
      <dc:date>2013-07-07T16:51:09Z</dc:date>
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