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    <title>topic &amp;gt;&amp;gt;&amp;gt;If you enable SMT in the in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Power-Consumption-varies-on-Sandy-Bridge-with-SMT-enabled/m-p/948155#M5137</link>
    <description>&lt;P&gt;&amp;gt;&amp;gt;&amp;gt;If you enable SMT in the bios, power consumption when idle (running sleep) on the system increases by .3%-1% (depending on system)&amp;gt;&amp;gt;&amp;gt;&lt;/P&gt;
&lt;P&gt;Do you mean per socket or per core?&lt;/P&gt;</description>
    <pubDate>Tue, 08 Oct 2013 17:56:37 GMT</pubDate>
    <dc:creator>Bernard</dc:creator>
    <dc:date>2013-10-08T17:56:37Z</dc:date>
    <item>
      <title>Power Consumption varies on Sandy-Bridge with SMT enabled/disabled</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Power-Consumption-varies-on-Sandy-Bridge-with-SMT-enabled/m-p/948152#M5134</link>
      <description>&lt;P&gt;I've found a strange phenomenon with Sandy-Bridge processors and am curious if anyone can answer why this occurs.&lt;/P&gt;
&lt;P&gt;If you enable SMT in the bios, power consumption when idle (running sleep) on the system increases by .3%-1% (depending on system). &amp;nbsp;These measurements come from running on dual-socketed Sandy-Bridge stand-alone servers and rack-based servers using a Watts-Up Pro device. &amp;nbsp;(Turbo is disabled in both cases.) &amp;nbsp;Are additional resources being powered when SMT is enabled in the bios?&lt;/P&gt;
&lt;P&gt;When running parallel benchmarks (NAS Parallel OpenMP), but only using as many threads as physical cores (16 in this case, 2 sockets, each 8-core Sandy-Bridge), I see a power increase of 2-3% with SMT enabled (in bios) over SMT disabled (in bios). &amp;nbsp;Using Intel's performance monitoring tools (pcm.x), I see L2 and L3 misses increase with SMT enabled over SMT disabled for some benchmakrs. &amp;nbsp;Using a custom tool for reading performance counters using PAPI, I find icache misses also increase sizably for a number of the parallel benchmarks. &amp;nbsp;Although these additional misses impact power, they rarely impact performance (max negative impact is ~.5% for the NPBs). The increase in icache misses (and subsequently L2/L3 misses) leads me to suspect that enabling SMT in the bios causes some form of icache resource partitionining between threads. &amp;nbsp;(This seems reasonable given the literature on resource partitioning to improve SMT performance.)&lt;/P&gt;
&lt;P&gt;My questions are: &amp;nbsp;1) Is resource partitiioning occurring (am I on the right track)? &amp;nbsp;2) Why would resource partitioning occur even if there is not active second thread? and 3) &amp;nbsp;What is being enabled/disabled to cause idle power consumption to increase when SMT is enabled in the bios?&lt;/P&gt;
&lt;P&gt;Thank you in advance,&lt;/P&gt;
&lt;P&gt;Leo&lt;/P&gt;</description>
      <pubDate>Sat, 05 Oct 2013 03:51:24 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Power-Consumption-varies-on-Sandy-Bridge-with-SMT-enabled/m-p/948152#M5134</guid>
      <dc:creator>Leonard_P_</dc:creator>
      <dc:date>2013-10-05T03:51:24Z</dc:date>
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    <item>
      <title>SMT involves resource</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Power-Consumption-varies-on-Sandy-Bridge-with-SMT-enabled/m-p/948153#M5135</link>
      <description>&lt;P&gt;SMT involves resource partitioning.&amp;nbsp; Some of the relevant resource are partioned dynamically, on demand, others (such as TLB) are split evenly.&amp;nbsp; If you didn't set affinity, your threads will swap resources frequently (incurring additional cache misses), and the vacated resources will take enough time to power down that your figures make sense.&amp;nbsp; I don't know that any expert on these questions is likely to be reading your post.&lt;/P&gt;</description>
      <pubDate>Sat, 05 Oct 2013 22:11:39 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Power-Consumption-varies-on-Sandy-Bridge-with-SMT-enabled/m-p/948153#M5135</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2013-10-05T22:11:39Z</dc:date>
    </item>
    <item>
      <title>Thanks Tim for the response.</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Power-Consumption-varies-on-Sandy-Bridge-with-SMT-enabled/m-p/948154#M5136</link>
      <description>&lt;P&gt;Thanks Tim for the response. &amp;nbsp;I am pinning the threads to specific cores and have used top to check the thread pinnings. &amp;nbsp;Is it possible that elements in addition to the TLB are being statically partitioned when SMT is enabled? &amp;nbsp;&lt;/P&gt;
&lt;P&gt;Also, any hunches on why there's more power consumption when just running "sleep"? &amp;nbsp;(sleep isn't being pinned but I don't think it needs to be?)&lt;/P&gt;
&lt;P&gt;Lastly, you said experts on SMT might not be monitoring these forums, is there a better place to ask the question?&lt;/P&gt;
&lt;P&gt;Thanks,&lt;/P&gt;
&lt;P&gt;Leo&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 07 Oct 2013 12:11:52 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Power-Consumption-varies-on-Sandy-Bridge-with-SMT-enabled/m-p/948154#M5136</guid>
      <dc:creator>Leonard_P_</dc:creator>
      <dc:date>2013-10-07T12:11:52Z</dc:date>
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    <item>
      <title>&gt;&gt;&gt;If you enable SMT in the</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Power-Consumption-varies-on-Sandy-Bridge-with-SMT-enabled/m-p/948155#M5137</link>
      <description>&lt;P&gt;&amp;gt;&amp;gt;&amp;gt;If you enable SMT in the bios, power consumption when idle (running sleep) on the system increases by .3%-1% (depending on system)&amp;gt;&amp;gt;&amp;gt;&lt;/P&gt;
&lt;P&gt;Do you mean per socket or per core?&lt;/P&gt;</description>
      <pubDate>Tue, 08 Oct 2013 17:56:37 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Power-Consumption-varies-on-Sandy-Bridge-with-SMT-enabled/m-p/948155#M5137</guid>
      <dc:creator>Bernard</dc:creator>
      <dc:date>2013-10-08T17:56:37Z</dc:date>
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