<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Strange perfomance variations on Xeon with hyperthreading (MMX/SSE2) in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Strange-perfomance-variations-on-Xeon-with-hyperthreading-MMX/m-p/960126#M5305</link>
    <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;I have optimized implementation of string alignment algorithm. I am using SSE2 intructions heavily that gives me on average 7 fold speedup. There is about 32 kb read only buffer thatis shared among multiple threads. Each thread requires individual read/write bufferof at most128Kb. Each thread also uses individual read only buffer with the size of about 64Kb.&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Now, the numbers I get:&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Higher number better (linear to the time)&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Single Xeon 2.8 box with HT enabled:&lt;/DIV&gt;
&lt;DIV&gt;single threadperfomance 312&lt;/DIV&gt;
&lt;DIV&gt;two thread perfomance:  604&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Dual Xeon 2.8 box with HT enabled:&lt;/DIV&gt;
&lt;DIV&gt;single thread perfomance: 295&lt;/DIV&gt;
&lt;DIV&gt;dual thread perfomance: 500&lt;/DIV&gt;
&lt;DIV&gt;three threads: 445&lt;/DIV&gt;
&lt;DIV&gt;four threads: 390&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Single P4 3.0 Box 2Mb cache with HT delivers:&lt;/DIV&gt;
&lt;DIV&gt;single threadperfomance: 295&lt;/DIV&gt;
&lt;DIV&gt;two thread perfomance: 500&lt;/DIV&gt;
&lt;DIV&gt;four thread pefomance: 460&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;My 1.7 Centrino laptop:&lt;/DIV&gt;
&lt;DIV&gt;single thread: 439&lt;/DIV&gt;
&lt;DIV&gt;two threads: 425&lt;/DIV&gt;
&lt;DIV&gt;three threads:425&lt;/DIV&gt;
&lt;DIV&gt;four threads:410&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Is there good explanation?&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;I am buffled. Something to do with cache?&lt;BR /&gt;Please help me to understand it.&lt;/DIV&gt;
&lt;P&gt;Message Edited by chum on &lt;SPAN class="date_text"&gt;11-28-2005&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;11:20 PM&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Message Edited by chum on &lt;SPAN class="date_text"&gt;11-28-2005&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;11:23 PM&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 29 Nov 2005 15:12:08 GMT</pubDate>
    <dc:creator>chum</dc:creator>
    <dc:date>2005-11-29T15:12:08Z</dc:date>
    <item>
      <title>Strange perfomance variations on Xeon with hyperthreading (MMX/SSE2)</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Strange-perfomance-variations-on-Xeon-with-hyperthreading-MMX/m-p/960126#M5305</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;I have optimized implementation of string alignment algorithm. I am using SSE2 intructions heavily that gives me on average 7 fold speedup. There is about 32 kb read only buffer thatis shared among multiple threads. Each thread requires individual read/write bufferof at most128Kb. Each thread also uses individual read only buffer with the size of about 64Kb.&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Now, the numbers I get:&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Higher number better (linear to the time)&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Single Xeon 2.8 box with HT enabled:&lt;/DIV&gt;
&lt;DIV&gt;single threadperfomance 312&lt;/DIV&gt;
&lt;DIV&gt;two thread perfomance:  604&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Dual Xeon 2.8 box with HT enabled:&lt;/DIV&gt;
&lt;DIV&gt;single thread perfomance: 295&lt;/DIV&gt;
&lt;DIV&gt;dual thread perfomance: 500&lt;/DIV&gt;
&lt;DIV&gt;three threads: 445&lt;/DIV&gt;
&lt;DIV&gt;four threads: 390&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Single P4 3.0 Box 2Mb cache with HT delivers:&lt;/DIV&gt;
&lt;DIV&gt;single threadperfomance: 295&lt;/DIV&gt;
&lt;DIV&gt;two thread perfomance: 500&lt;/DIV&gt;
&lt;DIV&gt;four thread pefomance: 460&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;My 1.7 Centrino laptop:&lt;/DIV&gt;
&lt;DIV&gt;single thread: 439&lt;/DIV&gt;
&lt;DIV&gt;two threads: 425&lt;/DIV&gt;
&lt;DIV&gt;three threads:425&lt;/DIV&gt;
&lt;DIV&gt;four threads:410&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Is there good explanation?&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;I am buffled. Something to do with cache?&lt;BR /&gt;Please help me to understand it.&lt;/DIV&gt;
&lt;P&gt;Message Edited by chum on &lt;SPAN class="date_text"&gt;11-28-2005&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;11:20 PM&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Message Edited by chum on &lt;SPAN class="date_text"&gt;11-28-2005&lt;/SPAN&gt; &lt;SPAN class="time_text"&gt;11:23 PM&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 29 Nov 2005 15:12:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Strange-perfomance-variations-on-Xeon-with-hyperthreading-MMX/m-p/960126#M5305</guid>
      <dc:creator>chum</dc:creator>
      <dc:date>2005-11-29T15:12:08Z</dc:date>
    </item>
  </channel>
</rss>

