topic Memory order machine clear conditions in Intel® Moderncode for Parallel Architectures https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Memory-order-machine-clear-conditions/m-p/961709#M5309 Can anyone explain how (and why) the pipeline is cleared due to memory ordering issues?<BR /><BR />Thanks. Tue, 27 Apr 2004 03:07:51 GMT Deleted_U_Intel 2004-04-27T03:07:51Z Memory order machine clear conditions https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Memory-order-machine-clear-conditions/m-p/961709#M5309 Can anyone explain how (and why) the pipeline is cleared due to memory ordering issues?<BR /><BR />Thanks. Tue, 27 Apr 2004 03:07:51 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Memory-order-machine-clear-conditions/m-p/961709#M5309 Deleted_U_Intel 2004-04-27T03:07:51Z