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    <title>topic Re: Prescient Loads in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Prescient-Loads/m-p/964564#M5390</link>
    <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;P&gt;Found this paper after I posted: &lt;/P&gt;
&lt;P&gt;&lt;A href="http://www.eecg.toronto.edu/~aamodt/papers/hw-support-prescientprefetch.hpca10.pdf" target="_blank"&gt;http://www.eecg.toronto.edu/~aamodt/papers/hw-support-prescientprefetch.hpca10.pdf&lt;/A&gt;&lt;/P&gt;
&lt;DIV&gt;Three of the five authors are Intel employees and the results were generated on a "research Itanium SMT". I expect, from the performance results cited in the paper, this technology may one day be included in Intel processors. Plenty of citations of related work are included for the curious.&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;-- clay&lt;/DIV&gt;</description>
    <pubDate>Tue, 06 Apr 2004 22:17:58 GMT</pubDate>
    <dc:creator>ClayB</dc:creator>
    <dc:date>2004-04-06T22:17:58Z</dc:date>
    <item>
      <title>Prescient Loads</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Prescient-Loads/m-p/964562#M5388</link>
      <description>Are they possible on Intel processors?  I'd explain what they were but this is about the 15th time I've typed this.</description>
      <pubDate>Fri, 02 Apr 2004 02:40:18 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Prescient-Loads/m-p/964562#M5388</guid>
      <dc:creator>jseigh</dc:creator>
      <dc:date>2004-04-02T02:40:18Z</dc:date>
    </item>
    <item>
      <title>Re: Prescient Loads</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Prescient-Loads/m-p/964563#M5389</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Joe -&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;I've left my Tarot cards at home, but I'm guessing that this is something different than pre-fetching? &lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;There are methods to begin a load on Itanium and, when the data is needed, check to determine if the load was completed and valid before using the data or blocking after re-starting the load if the original failed. These are known as &lt;EM&gt;speculative loads&lt;/EM&gt;, not prescient, though.&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;This sounds more like a topic for a hardware or processor design forum (which we don't have at the moment). &lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;-- clay&lt;/DIV&gt;</description>
      <pubDate>Tue, 06 Apr 2004 22:04:22 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Prescient-Loads/m-p/964563#M5389</guid>
      <dc:creator>ClayB</dc:creator>
      <dc:date>2004-04-06T22:04:22Z</dc:date>
    </item>
    <item>
      <title>Re: Prescient Loads</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Prescient-Loads/m-p/964564#M5390</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;P&gt;Found this paper after I posted: &lt;/P&gt;
&lt;P&gt;&lt;A href="http://www.eecg.toronto.edu/~aamodt/papers/hw-support-prescientprefetch.hpca10.pdf" target="_blank"&gt;http://www.eecg.toronto.edu/~aamodt/papers/hw-support-prescientprefetch.hpca10.pdf&lt;/A&gt;&lt;/P&gt;
&lt;DIV&gt;Three of the five authors are Intel employees and the results were generated on a "research Itanium SMT". I expect, from the performance results cited in the paper, this technology may one day be included in Intel processors. Plenty of citations of related work are included for the curious.&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;-- clay&lt;/DIV&gt;</description>
      <pubDate>Tue, 06 Apr 2004 22:17:58 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Prescient-Loads/m-p/964564#M5390</guid>
      <dc:creator>ClayB</dc:creator>
      <dc:date>2004-04-06T22:17:58Z</dc:date>
    </item>
    <item>
      <title>Re: Prescient Loads</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Prescient-Loads/m-p/964565#M5391</link>
      <description>Thanks.  It turns out what I was calling prescient loads would really be called out of order dependent loads.  There's a discussion about it in the Linux kernel mailing list here&lt;BR /&gt;&lt;BR /&gt;&lt;A href="http://marc.theaimsgroup.com/?t=100259422200002&amp;amp;r=1&amp;amp;w=2" target="_blank"&gt;http://marc.theaimsgroup.com/?t=100259422200002&amp;amp;r=1&amp;amp;w=2&lt;/A&gt;&lt;BR /&gt;&lt;BR /&gt;Apparently somebody went through the architecture manuals and decided that dependent loads would not do that.  They have a special Linux membar so they can use real membars for platforms that require it such as the Alpha.&lt;BR /&gt;&lt;BR /&gt;Joe Seigh</description>
      <pubDate>Fri, 09 Apr 2004 06:32:51 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Prescient-Loads/m-p/964565#M5391</guid>
      <dc:creator>jseigh</dc:creator>
      <dc:date>2004-04-09T06:32:51Z</dc:date>
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