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    <title>topic Re: lock prefix for logical cpus on the same physical cpu... in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/lock-prefix-for-logical-cpus-on-the-same-physical-cpu/m-p/967201#M5443</link>
    <description>&lt;DIV&gt;&lt;/DIV&gt;&lt;BR /&gt;
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&lt;DIV&gt;Could T1 and T2 use cmpxchg without a lock prefixto modify D?&lt;/DIV&gt;&lt;/DIV&gt;&lt;BR /&gt;
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&lt;DIV&gt;I think the answer is no, because cmpxchg does a redundant write that can probably be observed with the lock prefix...&lt;/DIV&gt;</description>
    <pubDate>Mon, 24 Oct 2005 13:31:55 GMT</pubDate>
    <dc:creator>Chris_M__Thomasson</dc:creator>
    <dc:date>2005-10-24T13:31:55Z</dc:date>
    <item>
      <title>lock prefix for logical cpus on the same physical cpu...</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/lock-prefix-for-logical-cpus-on-the-same-physical-cpu/m-p/967200#M5442</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;I think I know the answer already but I wanted to be sure. I believe that if you have two threads T1-T2that are bound toalogical processor LP1, they can atomically modifyper-processor data that is owned by LP1by using a cmpxchg without a lock-prefix. Now, here ismy question:&lt;/DIV&gt;
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&lt;DIV&gt;Given the following senerio:&lt;/DIV&gt;
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&lt;DIV&gt;Logicalprocessor LP1 isownedby core PC1 on physical processor P1&lt;/DIV&gt;
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&lt;DIV&gt;
&lt;DIV&gt;Logicalprocessor LP2 isownedby core PC1 on physical processor P1&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Per-processor data D is owned by PC1&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Thread T1 is bound to LP1&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;Thread T2 is bound to LP2&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;/DIV&gt;
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&lt;DIV&gt;Could T1 and T2 use cmpxchg without a lock prefixto modify D?&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Mon, 24 Oct 2005 12:53:30 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/lock-prefix-for-logical-cpus-on-the-same-physical-cpu/m-p/967200#M5442</guid>
      <dc:creator>Chris_M__Thomasson</dc:creator>
      <dc:date>2005-10-24T12:53:30Z</dc:date>
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    <item>
      <title>Re: lock prefix for logical cpus on the same physical cpu...</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/lock-prefix-for-logical-cpus-on-the-same-physical-cpu/m-p/967201#M5443</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;&lt;BR /&gt;
&lt;BLOCKQUOTE&gt;
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&lt;DIV&gt;Could T1 and T2 use cmpxchg without a lock prefixto modify D?&lt;/DIV&gt;&lt;/DIV&gt;&lt;BR /&gt;
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&lt;DIV&gt;I think the answer is no, because cmpxchg does a redundant write that can probably be observed with the lock prefix...&lt;/DIV&gt;</description>
      <pubDate>Mon, 24 Oct 2005 13:31:55 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/lock-prefix-for-logical-cpus-on-the-same-physical-cpu/m-p/967201#M5443</guid>
      <dc:creator>Chris_M__Thomasson</dc:creator>
      <dc:date>2005-10-24T13:31:55Z</dc:date>
    </item>
    <item>
      <title>Re: lock prefix for logical cpus on the same physical cpu...</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/lock-prefix-for-logical-cpus-on-the-same-physical-cpu/m-p/967202#M5444</link>
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lockfree wrote:&lt;BR /&gt;
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&lt;DIV&gt;
&lt;DIV&gt;Could T1 and T2 use cmpxchg without a lock prefixto modify D?&lt;/DIV&gt;&lt;/DIV&gt;&lt;BR /&gt;
&lt;HR /&gt;
&lt;/BLOCKQUOTE&gt;&lt;BR /&gt;
&lt;DIV&gt;I think the answer is no, because cmpxchg does a redundant write that can probably be observed with the lock prefix...&lt;/DIV&gt;&lt;BR /&gt;
&lt;HR /&gt;
&lt;/BLOCKQUOTE&gt;DOH! I mean't: cmpxchg does a redundant write that can probably be observed "without" the lock prefix... Sorry.&lt;BR /&gt;
&lt;DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Mon, 24 Oct 2005 13:34:01 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/lock-prefix-for-logical-cpus-on-the-same-physical-cpu/m-p/967202#M5444</guid>
      <dc:creator>Chris_M__Thomasson</dc:creator>
      <dc:date>2005-10-24T13:34:01Z</dc:date>
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    <item>
      <title>Re: lock prefix for logical cpus on the same physical cpu...</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/lock-prefix-for-logical-cpus-on-the-same-physical-cpu/m-p/967203#M5445</link>
      <description>&lt;DIV&gt;&lt;/DIV&gt;
&lt;P&gt;I posed this question to Phil Kerly, one of the Intel experts on Hyper-Threading. His response was that cmpxchg is NOT HT-safe without the 'lock' prefix. He sent a quick example that demonstrates this. I've attached the code to this post. &lt;/P&gt;
&lt;P&gt;
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Phil's instructions for using this demo code:
&lt;P&gt;&lt;/P&gt;
&lt;P class="MsoNormal"&gt;&lt;FONT face="Arial" color="navy" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: Arial"&gt;Find the line #define LOCK_EXAMPLE in the attached Windows file which I hacked together. You can uncomment this line to remove the lock prefix.&lt;NAMESPACE prefix="o" ns="urn:schemas-microsoft-com:office:office"&gt;&lt;P&gt;&lt;/P&gt;&lt;/NAMESPACE&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P class="MsoNormal"&gt;&lt;FONT face="Arial" color="navy" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: Arial"&gt;&lt;P&gt;&lt;/P&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P class="MsoNormal"&gt;&lt;FONT face="Arial" color="navy" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: Arial"&gt;With the lock prefix, the program will run indefinitely until you enter ctrl-C to stop it. Without the lock prefix, the program will terminate once is detects an unexpected condition.&lt;P&gt;&lt;/P&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P class="MsoNormal"&gt;&lt;FONT face="Arial" color="navy" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: Arial"&gt;&lt;P&gt;&lt;/P&gt;&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P class="MsoNormal"&gt;&lt;FONT face="Arial" color="navy" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: Arial"&gt;Two threads are created and affinitized to each of the logical HT processors. Each thread updates 16-bits of a 32-bit quantity using cmpxchg. One thread only updates the upper half. The other thread only updates the lower half. If at any time either thread detects that its portion does not match its expected value, the program will exit with a message stating that there has been a violation.&lt;/SPAN&gt;&lt;/FONT&gt;&lt;/P&gt;
&lt;P class="MsoNormal"&gt;&lt;FONT face="Arial" color="navy" size="2"&gt;&lt;SPAN style="FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: Arial"&gt;
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&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;I hope this helps.&lt;/P&gt;
&lt;P&gt;--clay&lt;/P&gt;
&lt;DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Sat, 19 Nov 2005 05:08:08 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/lock-prefix-for-logical-cpus-on-the-same-physical-cpu/m-p/967203#M5445</guid>
      <dc:creator>ClayB</dc:creator>
      <dc:date>2005-11-19T05:08:08Z</dc:date>
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