https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HT-on-the-new-Prescott-processor/m-p/974478#M5540 <DIV>For publicity purposes, they may be counting other changes since the original P4, such as the alleviation of the 64K aliasing problem, which could bea severe handicap to HT applications. Now, if you neglect to offset your stacks in a Windows application, for example, you should not immediately run into the aliasing problem. The aliasing problem now would occur with 1MB address intervals, so should not be so pervasive. Increased cache size also is likely to improve the effectiveness of HT in many applications.</DIV> Fri, 16 Jan 2004 05:27:59 GMT TimP 2004-01-16T05:27:59Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HT-on-the-new-Prescott-processor/m-p/974476#M5538 <DIV></DIV> <DIV></DIV> <DIV>Hi, I'm interested in the newly anounced Prescott processor( Pentium 4 extream edition with HT). </DIV> <DIV>But I wonder what's the difference between prescott's HT technology and its original versionbuilt in Pentium 4.</DIV> <DIV>I have been looking through this website, and found these words:</DIV> <DIV><STRONG></STRONG></DIV> <DIV><STRONG>Improved </STRONG><A href="http://www.intel.com/labs/features/ht11021.htm" target="_blank"><STRONG>Hyper-Threading Technology</STRONG></A>, including important enhancements to this innovation that make a single processor act like multiple processors to the operating system</DIV> <DIV></DIV> <DIV>But what is the important enhancements? It seems that Intel hasn't posted it on the site. Maybe someone here can help me. Thanks.</DIV> <P>Message Edited by RonnyZhang@hotmail.com on <SPAN class="date_text">01-15-2004</SPAN> <SPAN class="time_text">07:02 AM</SPAN></P><P>Message Edited by RonnyZhang@hotmail.com on <SPAN class="date_text">01-15-2004</SPAN> <SPAN class="time_text">07:05 AM</SPAN></P> Thu, 15 Jan 2004 22:59:02 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HT-on-the-new-Prescott-processor/m-p/974476#M5538 ronnyzhang 2004-01-15T22:59:02Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HT-on-the-new-Prescott-processor/m-p/974477#M5539 <DIV>Several changes in Prescott are intended to improve HT performance. For example, the increase in number of Write Combine buffers from 6 to 8 would permit HT threaded applications to write efficiently into 3 array sections within a single loop, where 2 was the previous limit.</DIV> Fri, 16 Jan 2004 01:29:40 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HT-on-the-new-Prescott-processor/m-p/974477#M5539 TimP 2004-01-16T01:29:40Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HT-on-the-new-Prescott-processor/m-p/974478#M5540 <DIV>For publicity purposes, they may be counting other changes since the original P4, such as the alleviation of the 64K aliasing problem, which could bea severe handicap to HT applications. Now, if you neglect to offset your stacks in a Windows application, for example, you should not immediately run into the aliasing problem. The aliasing problem now would occur with 1MB address intervals, so should not be so pervasive. Increased cache size also is likely to improve the effectiveness of HT in many applications.</DIV> Fri, 16 Jan 2004 05:27:59 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HT-on-the-new-Prescott-processor/m-p/974478#M5540 TimP 2004-01-16T05:27:59Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HT-on-the-new-Prescott-processor/m-p/974479#M5541 <DIV>Yes,this is one improvement, but not a significant change for just increasing in number of Write Combine buffers from 6 to 8. </DIV> <DIV>Is there a technical paper or manual telling us the architectual improvement of Precott's HT relative to P4?</DIV> Fri, 16 Jan 2004 15:46:53 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HT-on-the-new-Prescott-processor/m-p/974479#M5541 isn-removed938 2004-01-16T15:46:53Z