topic Re: IA64 xchg -- why only acquire? in Intel® Moderncode for Parallel Architectures

IA64 xchg -- why only acquire?

Intel_C_Intel — Wed, 12 Nov 2003 04:13:15 GMT

Please illuminate.

regards,
alexander.

Re: IA64 xchg -- why only acquire?

ClayB — Tue, 18 Nov 2003 01:10:22 GMT

Alexander -

Are you wondering about why only acquire semantics? Or are you wondering why not release, instead?

For me, I think this operation requires both, but I have no idea why acquire was chosen. I've looked through the three Itanium programming books I have. Only one addresses this issue and only then to define it as an acquire operation.

I'll see if I can pass you inquiry on to someone else more versed in Itanium processors.

-- clay

Re: IA64 xchg -- why only acquire?

terekhov — Thu, 04 Dec 2003 03:40:49 GMT

ClayB wrote:
Alexander -Are you wondering about why only acquire semantics?

Yes. I need release and all sort of other msync semantics. And also "naked" (no msync) atomic stuff, to begin with. In my book, op.acquire is "equivalent" to op.(hoist_load+hoist_store) and release is nothing but op.(sinkt_load+sink_store). I need less constrained atomic "op"-stuff as well. See http://tinyurl.com/xky8 and http://tinyurl.com/xky9.