topic Re: RCU+SMR, hazard pointers without memory barriers in Intel® Moderncode for Parallel Architectures

RCU+SMR, hazard pointers without memory barriers

jseigh — Wed, 29 Jun 2005 06:29:19 GMT

quick test before I spend another half hour typing in something that will disappear.

Re: RCU+SMR, hazard pointers without memory barriers

jseigh — Wed, 29 Jun 2005 06:37:54 GMT

There was some discussion here
http://www.ussg.iu.edu/hypermail/linux/kernel/0505.1/0252.html

I won't retype in my original post so as to not tempt the
activex daemons that lurk in Intel's html. :)

Re: RCU+SMR, hazard pointers without memory barriers

jseigh — Wed, 03 Aug 2005 09:11:03 GMT

You can find a working prototype at
http://sourceforge.net/projects/atomic-ptr-plus/
in the fastsmr package. It works on Linux for ia32 and for OS X for 32 bit powerpc. On a 866 mhz P3 a hazard pointer load with memory barriers is about 78 nsec and without memory barriers is about 11 nsec. On a 1.2 ghz ppc it's 115 and 10 nsec respectively. Not too bad when you let the pipelining do its stuff. This is probably the fastest lock-free read access method around that will scale well in a multiprocessor environment.