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    <title>topic HTM/STM and Scheduling in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HTM-STM-and-Scheduling/m-p/1000128#M6371</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;I have a question about Hardware and Software Transactional Memory.&lt;/P&gt;

&lt;P&gt;Given the types of versioning (eager and lazy) and conflict detection (optimistic and pessimistic) and let's say that 2 or more threads are performing a transaction that write/read the same memory location.&lt;/P&gt;

&lt;P&gt;The scheduling of the threads could affect the ability of detect a conflict? Which combination of versioning and conflict detection would be better to always catch the conflicts?&lt;/P&gt;

&lt;P&gt;Hope my question is clear.&lt;/P&gt;

&lt;P&gt;Thanks.&lt;BR /&gt;
	Best Regards,&lt;BR /&gt;
	Simone&lt;/P&gt;</description>
    <pubDate>Thu, 24 Apr 2014 01:25:45 GMT</pubDate>
    <dc:creator>Simone_A_</dc:creator>
    <dc:date>2014-04-24T01:25:45Z</dc:date>
    <item>
      <title>HTM/STM and Scheduling</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HTM-STM-and-Scheduling/m-p/1000128#M6371</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;I have a question about Hardware and Software Transactional Memory.&lt;/P&gt;

&lt;P&gt;Given the types of versioning (eager and lazy) and conflict detection (optimistic and pessimistic) and let's say that 2 or more threads are performing a transaction that write/read the same memory location.&lt;/P&gt;

&lt;P&gt;The scheduling of the threads could affect the ability of detect a conflict? Which combination of versioning and conflict detection would be better to always catch the conflicts?&lt;/P&gt;

&lt;P&gt;Hope my question is clear.&lt;/P&gt;

&lt;P&gt;Thanks.&lt;BR /&gt;
	Best Regards,&lt;BR /&gt;
	Simone&lt;/P&gt;</description>
      <pubDate>Thu, 24 Apr 2014 01:25:45 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HTM-STM-and-Scheduling/m-p/1000128#M6371</guid>
      <dc:creator>Simone_A_</dc:creator>
      <dc:date>2014-04-24T01:25:45Z</dc:date>
    </item>
    <item>
      <title>A Pessimistic control and</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HTM-STM-and-Scheduling/m-p/1000129#M6372</link>
      <description>&lt;P&gt;A Pessimistic control and Eager versioning would do good. As on a successful committ, the Eager versioning transaction would be updated directly into the address would perform a undo operation which avoids the concurrency conflict as the locations are locked down.&lt;/P&gt;

&lt;P&gt;and the Pessimistic control on transactions would provide a lock down on every place of location being involved in transaction closing a way for other users to change the logs.&lt;/P&gt;

&lt;P&gt;Hope you found it useful.&lt;/P&gt;</description>
      <pubDate>Thu, 25 Sep 2014 14:16:49 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/HTM-STM-and-Scheduling/m-p/1000129#M6372</guid>
      <dc:creator>Masood_Ali_M_</dc:creator>
      <dc:date>2014-09-25T14:16:49Z</dc:date>
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