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    <title>topic Haswell Transactional Memory read/write-set information in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Haswell-Transactional-Memory-read-write-set-information/m-p/1055501#M6845</link>
    <description>&lt;DIV class="post-text" itemprop="text"&gt;
	&lt;P&gt;Recently, Intel release haswell machines which support hardware transactional memory called transactional synchronization extension(TSX).&lt;/P&gt;

	&lt;P&gt;As Intel manual said, Speculative memory operations, write-set and read-set, are buffered in L1 cache and L2 cache each. (not exactly)&lt;/P&gt;

	&lt;P&gt;Then, Can I track transactional memory operations and get information like address, and values of read/write-set?&lt;/P&gt;
&lt;/DIV&gt;</description>
    <pubDate>Thu, 07 May 2015 07:42:03 GMT</pubDate>
    <dc:creator>YangHun_P_</dc:creator>
    <dc:date>2015-05-07T07:42:03Z</dc:date>
    <item>
      <title>Haswell Transactional Memory read/write-set information</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Haswell-Transactional-Memory-read-write-set-information/m-p/1055501#M6845</link>
      <description>&lt;DIV class="post-text" itemprop="text"&gt;
	&lt;P&gt;Recently, Intel release haswell machines which support hardware transactional memory called transactional synchronization extension(TSX).&lt;/P&gt;

	&lt;P&gt;As Intel manual said, Speculative memory operations, write-set and read-set, are buffered in L1 cache and L2 cache each. (not exactly)&lt;/P&gt;

	&lt;P&gt;Then, Can I track transactional memory operations and get information like address, and values of read/write-set?&lt;/P&gt;
&lt;/DIV&gt;</description>
      <pubDate>Thu, 07 May 2015 07:42:03 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Haswell-Transactional-Memory-read-write-set-information/m-p/1055501#M6845</guid>
      <dc:creator>YangHun_P_</dc:creator>
      <dc:date>2015-05-07T07:42:03Z</dc:date>
    </item>
    <item>
      <title>Hi YangHun,</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Haswell-Transactional-Memory-read-write-set-information/m-p/1055502#M6846</link>
      <description>&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Hi YangHun,&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;Intel® VTune™ Amplifier XE 2015 Update 2 added&amp;nbsp;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Intel® Transactional Synchronization Extensions (Intel® TSX) TSX Hotspots analysis. It&amp;nbsp;&lt;/SPAN&gt;provides&amp;nbsp;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;clockticks data for Haswell&amp;nbsp;&lt;/SPAN&gt;microarchitecture&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;. You can read more details about it &lt;A href="https://software.intel.com/en-us/articles/whats-new-intel-vtune-amplifier-xe-2015-update-2#tsx-hotspots"&gt;here&lt;/A&gt;.&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;Hope it helps.&lt;/P&gt;</description>
      <pubDate>Wed, 27 May 2015 04:24:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Haswell-Transactional-Memory-read-write-set-information/m-p/1055502#M6846</guid>
      <dc:creator>gaston-hillar</dc:creator>
      <dc:date>2015-05-27T04:24:17Z</dc:date>
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