https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Memory-fences/m-p/803053#M686 asm volatile("":::"memory"); merely prevents the compiler's optimizer from rearranging your code --- reads and writes that appear in source before that asm block must appear as CPU instructions before that asm block, and reads and writes that appear in source after that asm block must appear as CPU instructions after that asm block. The CPU may still reorder these reads and writes, and they may become visible to other CPUs in the system out of order (but constrained by the CPU memory model).<BR /><BR />__sync_synchronize() will generate a suitable CPU instruction to generate a memory fence. On Intel CPUs this may be an MFENCE instruction, or a LOCKed instruction such as XCHG. This has the additional consequence of imposing visibility constraints on the memory accesses at the CPU level.<BR /> Mon, 20 Jun 2011 11:44:20 GMT anthony_williams 2011-06-20T11:44:20Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Memory-fences/m-p/803052#M685 Hello, <BR /><BR />Just a quick question regarding memory fences in C.<BR />What exactly is the difference (if any) between:<BR />__sync_synchronize();<BR />asm volatile("":::"memory");<BR /> Sat, 18 Jun 2011 14:52:55 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Memory-fences/m-p/803052#M685 Tudor 2011-06-18T14:52:55Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Memory-fences/m-p/803053#M686 asm volatile("":::"memory"); merely prevents the compiler's optimizer from rearranging your code --- reads and writes that appear in source before that asm block must appear as CPU instructions before that asm block, and reads and writes that appear in source after that asm block must appear as CPU instructions after that asm block. The CPU may still reorder these reads and writes, and they may become visible to other CPUs in the system out of order (but constrained by the CPU memory model).<BR /><BR />__sync_synchronize() will generate a suitable CPU instruction to generate a memory fence. On Intel CPUs this may be an MFENCE instruction, or a LOCKed instruction such as XCHG. This has the additional consequence of imposing visibility constraints on the memory accesses at the CPU level.<BR /> Mon, 20 Jun 2011 11:44:20 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Memory-fences/m-p/803053#M686 anthony_williams 2011-06-20T11:44:20Z