topic Seems reasonable. You could in Intel® Moderncode for Parallel Architectures

Aligned loads + shift vs. unaligned loads vs. vgather

Mark_D_9 — Wed, 18 May 2016 15:40:12 GMT

What do you recommend would be the best approach for this stencil on a Xeon Phi? The idea is:

Given a 1-D array A: [0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18]

And three scalars: probUp, probMid, probDown

You need to compute a 1-D array B where:

B[0] = probDown*A[0] + probMid*A[1] + probUp*A[2]

B[1] = probDown*A[1] + probMid*A[2] + probUp*A[3]

B[2] = probDown*A[2] + probMid*A[3] + probUp*A[4]

etc…

Everything is double precision.

The approach I’m going with is to load three vector registers, a0, a1, and a2 (where a0 is aligned to the loop iterator, a1 is shifted by 1 element, and a2 is shifted by 2 elements), do muls and fmadds to smoosh them together with the scalars, and then store.

The only question I guess I have is what would they say the most efficient way is to get the a* vector registers loaded from memory. I’m pretty sure it’s best to do two loads and some shifts (as I’m doing below) as opposed to doing unaligned loads or using gather intrinsics, but I’d be curious if Intel has a different opinion.

Seems reasonable. You could

TimP — Wed, 18 May 2016 16:33:05 GMT

Seems reasonable. You could write c or Fortran with alignment assertions

So, which is the most optimal

Mark_D_9 — Wed, 18 May 2016 16:35:56 GMT

So, which is the most optimal approach? Aligned loads with shifts, or unaligned loads, or using gather intrinsics?

The posted papers discussing

TimP — Thu, 19 May 2016 12:13:00 GMT

The posted papers discussing -qopt-assume-safe-padding are relevant. Compilers use gather and scatter to access partial cache lines only to prevent possible unsafe access outside the array. Unaligned access may be the slowest.

You might get attention from experts if you would ask on the Intel Xeon phi forum.