MSR and pcm-msr.x

hpcdkhab — Tue, 17 Jan 2017 20:04:19 GMT

Dear supporter,

I would like to use pcm-msr.x for various msr registers, which are described in the datasheets for Intel Xeon E5 v2 and v3 (volume 2), for example the register MEM_ACCUMULATED_BW_CH_[0:3].
Unfortunately, I couldn't find any information about addresses of the registers, which I have to use as the last parameter in the command line of pcm-msr.x (except a small list under the link http://www.vi-hps.org/upload/program/espt-sc14/vi-hps-ESPT14-Shoga.pdf ).

Thank you,

Dmitry

Unfortunately these

McCalpinJohn — Tue, 17 Jan 2017 22:09:17 GMT

Unfortunately these configuration registers described in the datasheet are not MSRs -- they are addresses in PCI configuration space. These addresses may or may not be restricted to BIOS/SMM access, and they tend to be minimally documented. The documentation assumes some familiarity with the PCI configuration space structure and naming conventions, so it is easy to get confused.

A document that is typically more user-friendly is the "Intel Xeon Processor E5 and E7 v3 Family Uncore Performance Monitoring Reference Manual" (document 331051), along with the corresponding documents for older and newer Xeon E5 processors. These documents describe how to program and access both MSR-based and PCI-configuration-space-based performance counters in the processor uncore. Unlike the registers described in Volume 2 of the product datasheets, these performance monitor registers are intended to be accessible from the OS (with root access permissions).

topic Unfortunately these in Intel® Moderncode for Parallel Architectures

MSR and pcm-msr.x

Unfortunately these