<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic How to manipulate a &amp;quot;thread-scoped&amp;quot; MSR? in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-manipulate-a-quot-thread-scoped-quot-MSR/m-p/1101887#M7300</link>
    <description>&lt;P&gt;I am trying to understand how Machine Check Architecture (MCA) works. It consists of a set of global configuration/status MSRs and several bank of MSRs for error logging.&lt;/P&gt;

&lt;P&gt;In Intel Manual Vol.3 Ch.35, I see some MCA global MSRs are "&lt;STRONG&gt;thread-scoped&lt;/STRONG&gt;", such as:&lt;/P&gt;

&lt;P&gt;&lt;STRONG&gt;IA32_MCG_STATUS&lt;/STRONG&gt; (0x17AH) in Xeon Phi processor.&lt;/P&gt;

&lt;P&gt;The manual says in Vol.3. Ch.35.6:&lt;/P&gt;

&lt;P&gt;&lt;STRONG&gt;&lt;SPAN class="fontstyle0"&gt;“Thread” means this bit field must be programmed on each logical processor independently.&lt;/SPAN&gt;&lt;/STRONG&gt;&lt;BR style=" font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-align: -webkit-auto; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; " /&gt;
	&amp;nbsp;&lt;/P&gt;

&lt;P&gt;So, if I want to manipulate some bits of a thread-scoped MSR, I have to make sure that &lt;STRONG&gt;the code containing the manipulation logic is executed on the logical processor which owns that thread-scoped MSR&lt;/STRONG&gt;.&amp;nbsp;&lt;/P&gt;

&lt;P&gt;And although the thread-scoped MSR has only one fixed address (e.g. 0x17AH for IA32_MCG_STATUS), visit this &lt;STRONG&gt;same &lt;/STRONG&gt;address on different logical processor will visit &lt;STRONG&gt;different &lt;/STRONG&gt;MSRs.&lt;/P&gt;

&lt;P&gt;Is my understanding right?&lt;/P&gt;

&lt;P&gt;If so, how can I designate which logical processor to run my code?&amp;nbsp; For example, I want to write to a thread-scoped MCA MSR so that I can inject/spoof some hardware error to validate the whole error handling stack.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 01 Dec 2016 14:29:15 GMT</pubDate>
    <dc:creator>sm_w_</dc:creator>
    <dc:date>2016-12-01T14:29:15Z</dc:date>
    <item>
      <title>How to manipulate a "thread-scoped" MSR?</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-manipulate-a-quot-thread-scoped-quot-MSR/m-p/1101887#M7300</link>
      <description>&lt;P&gt;I am trying to understand how Machine Check Architecture (MCA) works. It consists of a set of global configuration/status MSRs and several bank of MSRs for error logging.&lt;/P&gt;

&lt;P&gt;In Intel Manual Vol.3 Ch.35, I see some MCA global MSRs are "&lt;STRONG&gt;thread-scoped&lt;/STRONG&gt;", such as:&lt;/P&gt;

&lt;P&gt;&lt;STRONG&gt;IA32_MCG_STATUS&lt;/STRONG&gt; (0x17AH) in Xeon Phi processor.&lt;/P&gt;

&lt;P&gt;The manual says in Vol.3. Ch.35.6:&lt;/P&gt;

&lt;P&gt;&lt;STRONG&gt;&lt;SPAN class="fontstyle0"&gt;“Thread” means this bit field must be programmed on each logical processor independently.&lt;/SPAN&gt;&lt;/STRONG&gt;&lt;BR style=" font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: 2; text-align: -webkit-auto; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-size-adjust: auto; -webkit-text-stroke-width: 0px; " /&gt;
	&amp;nbsp;&lt;/P&gt;

&lt;P&gt;So, if I want to manipulate some bits of a thread-scoped MSR, I have to make sure that &lt;STRONG&gt;the code containing the manipulation logic is executed on the logical processor which owns that thread-scoped MSR&lt;/STRONG&gt;.&amp;nbsp;&lt;/P&gt;

&lt;P&gt;And although the thread-scoped MSR has only one fixed address (e.g. 0x17AH for IA32_MCG_STATUS), visit this &lt;STRONG&gt;same &lt;/STRONG&gt;address on different logical processor will visit &lt;STRONG&gt;different &lt;/STRONG&gt;MSRs.&lt;/P&gt;

&lt;P&gt;Is my understanding right?&lt;/P&gt;

&lt;P&gt;If so, how can I designate which logical processor to run my code?&amp;nbsp; For example, I want to write to a thread-scoped MCA MSR so that I can inject/spoof some hardware error to validate the whole error handling stack.&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 01 Dec 2016 14:29:15 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-manipulate-a-quot-thread-scoped-quot-MSR/m-p/1101887#M7300</guid>
      <dc:creator>sm_w_</dc:creator>
      <dc:date>2016-12-01T14:29:15Z</dc:date>
    </item>
    <item>
      <title>The details will depend on</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-manipulate-a-quot-thread-scoped-quot-MSR/m-p/1101888#M7301</link>
      <description>&lt;P&gt;The details will depend on your OS and whether you are running in the kernel or in user space....&lt;/P&gt;

&lt;P&gt;If you are running on a Linux system, running in user space, you can use the /dev/cpu/&lt;N&gt;/msr device driver interface to handle the core mapping for you.&amp;nbsp; E.g., if you want to read an MSR on logical processor 3, you open /dev/cpu/3/msr and perform a "pread()" operation using the MSR number as the "offset" parameter.&amp;nbsp;&amp;nbsp;&amp;nbsp; I recommend downloading the msr-tools 1.3 package from &lt;A href="https://01.org/msr-tools" target="_blank"&gt;https://01.org/msr-tools&lt;/A&gt; and seeing how the "rdmsr.c" and "wrmsr.c" command-line utilities perform these simple operations.&lt;/N&gt;&lt;/P&gt;

&lt;P&gt;If you are on a Linux system and running in kernel space (e.g., inside a device driver), there are helper routines defined to execute the RDMSR instruction on a target logical processor.&amp;nbsp; In the 3.10 kernels that I use the interfaces are "rdmsr_safe_on_cpu()" and "wrmsr_safe_on_cpu()".&amp;nbsp; These interfaces set up the inter-processor interrupts necessary to start up a kernel process on the target core and have it read the MSR on that core, then return the value to the calling process.&lt;/P&gt;</description>
      <pubDate>Thu, 01 Dec 2016 19:06:22 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/How-to-manipulate-a-quot-thread-scoped-quot-MSR/m-p/1101888#M7301</guid>
      <dc:creator>McCalpinJohn</dc:creator>
      <dc:date>2016-12-01T19:06:22Z</dc:date>
    </item>
  </channel>
</rss>

