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    <title>topic Questions on these topics in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/TSX-RTM-Related-Question/m-p/1103810#M7352</link>
    <description>&lt;P&gt;Questions on these topics seem more likely to get answers on the ISA forum&lt;/P&gt;

&lt;P&gt;&lt;A href="https://software.intel.com/en-us/forums/intel-isa-extensions" target="_blank"&gt;https://software.intel.com/en-us/forums/intel-isa-extensions&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;There is also a collection of references&lt;/P&gt;

&lt;P&gt;&lt;A href="https://software.intel.com/en-us/blogs/2013/06/07/web-resources-about-intelr-transactional-synchronization-extensions" target="_blank"&gt;https://software.intel.com/en-us/blogs/2013/06/07/web-resources-about-intelr-transactional-synchronization-extensions&lt;/A&gt;&lt;/P&gt;</description>
    <pubDate>Wed, 09 Mar 2016 12:07:00 GMT</pubDate>
    <dc:creator>TimP</dc:creator>
    <dc:date>2016-03-09T12:07:00Z</dc:date>
    <item>
      <title>TSX RTM Related Question</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/TSX-RTM-Related-Question/m-p/1103809#M7351</link>
      <description>&lt;P&gt;Hello, everyone, I just start to learn RTM programming.&lt;/P&gt;

&lt;P&gt;I have some questions about RTM. Take the following code for example(from: &lt;A href="http://lwn.net/Articles/533894/)" target="_blank"&gt;http://lwn.net/Articles/533894/)&lt;/A&gt;, if the lock is not free, then it will execute _xabort, and return abort state 0xff. Will the program go back to execute _xbegin again, and found the&amp;nbsp;&lt;SPAN style="font-size: 13.008px; line-height: 11.1497px;"&gt;_xbegin is no equal to _XBEGIN_STARTED, then it will execute fallback handler. Is my understanding right?&lt;/SPAN&gt;&lt;/P&gt;

&lt;PRE class="brush:cpp;"&gt;if ((status = _xbegin()) == _XBEGIN_STARTED){	/* Start transaction */
	    if (lock is free)	/* Check lock and put into read-set */
		return;		/* Execute lock region in transaction */
	
	    _xabort(0xff);		/* Abort transaction as lock is busy */
}else{				
	/* fallback handler */
}&lt;/PRE&gt;

&lt;P&gt;Also, I saw two&amp;nbsp;RTM Abort Status Definition in&amp;nbsp;&lt;A href="http://intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf"&gt;&lt;STRONG&gt;&lt;EM&gt;Intel® 64 and IA-32 Architectures&amp;nbsp;Optimization Reference Manual&lt;/EM&gt;&lt;/STRONG&gt;&lt;/A&gt;(&lt;SPAN style="font-size: 13.008px; line-height: 11.1497px;"&gt;Table 12-1. RTM Abort Status Definition) and &lt;/SPAN&gt;Intel® 64 and &lt;STRONG&gt;&lt;EM&gt;&lt;A href="http://intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf"&gt;IA-32 Architectures&amp;nbsp;Software Developer’s Manual&lt;/A&gt;&lt;/EM&gt;&lt;/STRONG&gt;&lt;SPAN style="font-size: 13.008px; line-height: 11.1497px;"&gt;(&lt;/SPAN&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;Table 15-1. RTM Abort Status Definition). It seems that they are different, but I did not quite understand. &lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;&lt;SPAN style="font-size: 1em; line-height: 1.5;"&gt;I know if the lock is not free, we should set abort status to 0xff. Is that any other situation that abort status will be automatically set to 0xff? How could we distinguish TM region is abort because of lock is not free and other events that cause automatically abort? Also, I found the status return value could be 0 and 8. Is there any different there?&lt;/SPAN&gt;&lt;/P&gt;

&lt;P&gt;Thanks a lot in advance!&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;

&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 08 Mar 2016 23:32:32 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/TSX-RTM-Related-Question/m-p/1103809#M7351</guid>
      <dc:creator>Shu_W_</dc:creator>
      <dc:date>2016-03-08T23:32:32Z</dc:date>
    </item>
    <item>
      <title>Questions on these topics</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/TSX-RTM-Related-Question/m-p/1103810#M7352</link>
      <description>&lt;P&gt;Questions on these topics seem more likely to get answers on the ISA forum&lt;/P&gt;

&lt;P&gt;&lt;A href="https://software.intel.com/en-us/forums/intel-isa-extensions" target="_blank"&gt;https://software.intel.com/en-us/forums/intel-isa-extensions&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;There is also a collection of references&lt;/P&gt;

&lt;P&gt;&lt;A href="https://software.intel.com/en-us/blogs/2013/06/07/web-resources-about-intelr-transactional-synchronization-extensions" target="_blank"&gt;https://software.intel.com/en-us/blogs/2013/06/07/web-resources-about-intelr-transactional-synchronization-extensions&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 09 Mar 2016 12:07:00 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/TSX-RTM-Related-Question/m-p/1103810#M7352</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2016-03-09T12:07:00Z</dc:date>
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