topic How to optimize this uPipe diagram? in Intel® Moderncode for Parallel Architectures

How to optimize this uPipe diagram?

sun__lei — Mon, 28 Oct 2019 06:25:31 GMT

Look at the attachment. How to optimize this uPipe diagram?

It would help if you would

jimdempseyatthecove — Mon, 28 Oct 2019 11:57:39 GMT

It would help if you would show the sections of the code that is giving you this result.

Jim Dempsey

Quote:jimdempseyatthecove

sun__lei — Mon, 28 Oct 2019 12:10:10 GMT

jimdempseyatthecove (Blackbelt) wrote:
It would help if you would show the sections of the code that is giving you this result.
Jim Dempsey

Sorry, the code belongs to my company and the code is too long. In a nutshell, the code has much random memory access. I have tried many optimization methods such as prefetch，but all failed. I don't know whether I have inserted the right prefetch position or prefetch size. Maybe you have a better solution.

Thanks for your reply very much. :)

I have found that the

jimdempseyatthecove — Mon, 28 Oct 2019 15:04:46 GMT

I have found that the hardware pre-fetch capability of modern CPUs makes it in most cases counter-productive to introduce software prefetching.

The better solution is (often) to analyze your algorithms and data placement, and if possible rearrange data and restructure the algorithm (without adversely affecting results) such that the CPU can get more work done per memory fetch. Note, memory is fetched by cache line (or double cache line).

If you are unable to resolve this by yourself, then you can contact me and we can work something out under NDA.

Jim Dempsey

Quote:jimdempseyatthecove

sun__lei — Mon, 28 Oct 2019 15:22:37 GMT

jimdempseyatthecove (Blackbelt) wrote:
I have found that the hardware pre-fetch capability of modern CPUs makes it in most cases counter-productive to introduce software prefetching.
The better solution is (often) to analyze your algorithms and data placement, and if possible rearrange data and restructure the algorithm (without adversely affecting results) such that the CPU can get more work done per memory fetch. Note, memory is fetched by cache line (or double cache line).
If you are unable to resolve this by yourself, then you can contact me and we can work something out under NDA.
Jim Dempsey

Yeah, I have optimized my algorithm and data placement as much as possible. Next, I want to use AVX to try to solve the uPipe diagram. Do you think AVX can help? It is my pleasure to be able to communicate with you. What is your contact? We can keep in touch and exchange some problems.

Depending on your code, data

jimdempseyatthecove — Tue, 29 Oct 2019 12:41:21 GMT

Depending on your code, data organization and optimizations selected, your code may already be using multiple lanes of the AVX registers.

Jim Dempsey