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    <title>topic On Sandy Bridge (and other in Intel® Moderncode for Parallel Architectures</title>
    <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Hyper-threading-on-Skylake/m-p/1142415#M7761</link>
    <description>&lt;P&gt;On Sandy Bridge (and other CPU models beginning at least since Nehalem), only 64 ITLB entries were available with HT disabled.&amp;nbsp; There is more information about TLB changes for Skylake at &lt;A href="https://en.wikichip.org/wiki/intel/microarchitectures/skylake" target="_blank"&gt;https://en.wikichip.org/wiki/intel/microarchitectures/skylake&lt;/A&gt; .&amp;nbsp; This seems to agree with your finding that the partitioning of TLB other than ITLB wasn't changed, although there are several changes in associativity.&lt;/P&gt;

&lt;P&gt;I guess you are talking about Skylake client CPU.&lt;/P&gt;</description>
    <pubDate>Thu, 13 Jul 2017 10:49:17 GMT</pubDate>
    <dc:creator>TimP</dc:creator>
    <dc:date>2017-07-13T10:49:17Z</dc:date>
    <item>
      <title>Hyper threading on Skylake</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Hyper-threading-on-Skylake/m-p/1142414#M7760</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;

&lt;P&gt;I have some questions about the resources shared among logical cores on Skylake processors. I found the Intel manual here: &lt;A href="https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf" target="_blank"&gt;https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf&lt;/A&gt;&lt;/P&gt;

&lt;P&gt;On page 36, Table 2-5 demonstrates that the ITLB is dynamically partitioned, while all other levels of TLBs are fixed partitioned. As far as I know on Sandy Bridge, the configurations are the opposite, where "the ITLB is partitioned 50/50 statically under HT, DTLB and shared TLB are partitioned on demand, not necessarily 50/50" (https://software.intel.com/en-us/forums/intel-moderncode-for-parallel-architectures/topic/281287).&lt;/P&gt;

&lt;P&gt;According to my experiment on I7-6700k (skylake), it is inline with Sandy Bridge. For a brief explanation, I used cpuid to query the number of TLB entries. While HT is enabled, 64/64/1536 entries are available for ITLB/DTLB/STLB respectively; while HT is disabled, 128/64/1536 entries are available.&lt;/P&gt;

&lt;P&gt;This really confuses me. Thanks&lt;/P&gt;</description>
      <pubDate>Fri, 07 Jul 2017 14:32:03 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Hyper-threading-on-Skylake/m-p/1142414#M7760</guid>
      <dc:creator>yunfeng7854</dc:creator>
      <dc:date>2017-07-07T14:32:03Z</dc:date>
    </item>
    <item>
      <title>On Sandy Bridge (and other</title>
      <link>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Hyper-threading-on-Skylake/m-p/1142415#M7761</link>
      <description>&lt;P&gt;On Sandy Bridge (and other CPU models beginning at least since Nehalem), only 64 ITLB entries were available with HT disabled.&amp;nbsp; There is more information about TLB changes for Skylake at &lt;A href="https://en.wikichip.org/wiki/intel/microarchitectures/skylake" target="_blank"&gt;https://en.wikichip.org/wiki/intel/microarchitectures/skylake&lt;/A&gt; .&amp;nbsp; This seems to agree with your finding that the partitioning of TLB other than ITLB wasn't changed, although there are several changes in associativity.&lt;/P&gt;

&lt;P&gt;I guess you are talking about Skylake client CPU.&lt;/P&gt;</description>
      <pubDate>Thu, 13 Jul 2017 10:49:17 GMT</pubDate>
      <guid>https://community.intel.com/t5/Intel-Moderncode-for-Parallel/Hyper-threading-on-Skylake/m-p/1142415#M7761</guid>
      <dc:creator>TimP</dc:creator>
      <dc:date>2017-07-13T10:49:17Z</dc:date>
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