https://community.intel.com/t5/Intel-Moderncode-for-Parallel/FPGA-Fitter-Chipplaner-quot-set-instance-assignment-name-REGION/m-p/1721764#M8229 <P>We aim to optimize the timing by restricting the routing area, and by limiting the placement positions and positional relationships of each module on the chip. We used the&nbsp;&nbsp;<STRONG>set_instance_assignment -name REGION "X20 Y230 X380 Y280" -to "top0_name|u_top1_entity_name|u_top2_entity_name"&nbsp;</STRONG>&nbsp;statement on Quartus 24.3, but it seems to have no effect. Is it because the grammar we used is incorrect? Can anyone provide assistance?</P> Mon, 13 Oct 2025 09:32:04 GMT Lingyi 2025-10-13T09:32:04Z https://community.intel.com/t5/Intel-Moderncode-for-Parallel/FPGA-Fitter-Chipplaner-quot-set-instance-assignment-name-REGION/m-p/1721764#M8229 <P>We aim to optimize the timing by restricting the routing area, and by limiting the placement positions and positional relationships of each module on the chip. We used the&nbsp;&nbsp;<STRONG>set_instance_assignment -name REGION "X20 Y230 X380 Y280" -to "top0_name|u_top1_entity_name|u_top2_entity_name"&nbsp;</STRONG>&nbsp;statement on Quartus 24.3, but it seems to have no effect. Is it because the grammar we used is incorrect? Can anyone provide assistance?</P> Mon, 13 Oct 2025 09:32:04 GMT https://community.intel.com/t5/Intel-Moderncode-for-Parallel/FPGA-Fitter-Chipplaner-quot-set-instance-assignment-name-REGION/m-p/1721764#M8229 Lingyi 2025-10-13T09:32:04Z