Concept AI PC SoC: Shared SLC + NPU-Assisted Gaming — Looking for Architecture Feedback

SamuelChung — Fri, 23 Jan 2026 15:03:32 GMT

Hello,

I’m a Grade 10 student with a keen interest in SoC architecture and power-efficient computing. Recently, I worked on a concept-level AI PC SoC design as a learning project, and I’d really appreciate technical feedback from experienced engineers.

This is not a product proposal, just an attempt to explore architectural trade-offs specific to thin-and-light AI PCs.

My key design focuses are:

A 128 MB system-level shared cache (SLC) for the CPU, GPU and NPU, intended to reduce DRAM traffic
NPU-assisted gaming – offloading frame generation and super-resolution from the GPU to improve energy efficiency
A unified CPU core microarchitecture, where performance and efficiency are differentiated mainly by frequency, voltage curves and feature trimming

My core question is this: Can AI accelerators and large shared caches meaningfully reduce GPU power consumption in portable gaming workloads?

I’ve summarized the design assumptions, power targets and potential risks in the attached PDF, and I’d be particularly grateful for your feedback on these points:

Whether the shared SLC approach is realistic at this scale
Practical limitations of involving an NPU in real-time gaming pipelines
Any obvious architectural blind spots in my core assumptions

Thank you for your time – any insights or corrections you can offer would mean a lot.

be grateful for any insights or corrections.

topic Concept AI PC SoC: Shared SLC + NPU-Assisted Gaming — Looking for Architecture Feedback in Intel® Moderncode for Parallel Architectures

Concept AI PC SoC: Shared SLC + NPU-Assisted Gaming — Looking for Architecture Feedback